公开(公告)号：CA1111922A

公开(公告)日：1981-11-03

申请号：CA292567

申请日：1977-12-07

Applicant: IBM

Inventor： AMES RICHARD N ,  HARDIN DICK K ,  LEININGER JOEL C ,  TAYLOR GEORGE P

IPC: G06F13/12 ,  G06F7/00 ,  G06F9/38 ,  G06F13/38 ,  G06F15/16 ,  G06F15/17 ,  G06F15/177 ,  G06F3/00

Abstract: SYNCHRONOUS MICROCODE GENERATED INTERFACE FOR SYSTEM OF MICROCODED DATA PROCESSORS An interface comprising normal asynchronous I/O interface hardware in combination with certain additional synchronizing connections is provided between a microcoded central processing unit (CPU) and a microcoded secondary processor (such as a floating point processor) for enabling these processors to function conjointly under common timing control as though they were natively attached to each other insofar as the execution of their respective mocrocodes is concerned. The secondary processor shares the normal I/O interface with the I/O devices for data transfer purposes in such fashion that data can be transferred between any of the I/O devices and the CPU in cycle steal mode when the secondary processor is internally occupied with executing an operation delegated to it by the central processor, and when the secondary processor is ready to store data which it has produced, I/O data transfers in cycle steal mode can be made concurrently with data transfers between the secondary processor and the CPU on a demand multiplex basis. Coordinating signals are passed between the processors at certain steps during the execution of their respective microcodes to maintain these microcodes in proper timed relationship with each other.

公开(公告)号：CA1143855A

公开(公告)日：1983-03-29

申请号：CA360339

申请日：1980-09-16

Applicant: IBM

Inventor： HARDIN DICK K ,  PUTTLITZ FREDERIC J

IPC: G06F15/16 ,  G06F12/00 ,  G06F13/18 ,  G06F15/177 ,  G06F13/00

Abstract: A system is provided that includes a plurality of processors connected to a shared storage via an asynchronous storage interface that includes various interface logic and a ring counter that performs polling of the processors for access to the shared storage. The ring utilizes a "lookahead" feature that bypasses stages in the ring to speed up responses to request signals from the processor. The logic uses the clock from the particular processor accessing the shared memory at any point in time. BC9-78-026

公开(公告)号：FR2389175A1

公开(公告)日：1978-11-24

申请号：FR7809976

申请日：1978-03-28

Applicant: IBM

Inventor： AMES RICHARD N ,  HARDIN DICK K ,  LEININGER JOEL C ,  TAYLOR GEORGE P

IPC: G06F13/12 ,  G06F7/00 ,  G06F9/38 ,  G06F13/38 ,  G06F15/16 ,  G06F15/17 ,  G06F15/177 ,  G06F13/00

Abstract: An interface comprising normal asynchronous I/O interface hardware in combination with certain additional synchronizing connections is provided between a microcoded central processing unit (CPU) and a microcoded secondary processor (such as a floating point processor) for enabling these processors to function conjointly under common timing control as though they were natively attached to each other insofar as the execution of their respective microcodes is concerned. The secondary processor shares the normal I/O interface with the I/O devices for data transfer purposes in such fashion that data can be transferred between any of the I/O devices and the CPU in cycle steal mode when the secondary processor is internally occupied with executing an operation delegated to it by the central processor, and when the secondary processor is ready to store data which it has produced, I/O data transfers in cycle steal mode can be made concurrently with data transfers between the secondary processor and the CPU on a demand multiplex basis. Coordinating signals are passed between the processors at certain steps during the execution of their respective microcodes to maintain these microcodes in proper timed relationship with each other.