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公开(公告)号：DE69022411D1
公开(公告)日：1995-10-19
申请号：DE69022411
申请日：1990-06-29
Applicant: IBM
Inventor： ABBIATE JEAN-CLAUDE , QUENEL LUCIEN
Abstract: A system implemented in a Data Circuit Terminating Equipment (DCE), interfacing between a user's data processing equipment and a digital network, comprises well-known means for generating Analog Carrier Detect (ACD) DCE internal signal (ACD is 'up' if energy is detected on the DCE receive line), as well as Analog Squared Data (ASD) DCE internal signal (each ASD square pulse corresponds to a positive or a negative pulse on the DCE receive line), and ASD WIDTH ERROR DCE internal signal (ASD WIDTH ERROR is 'up' anytime an ASD square pulse is found to have either a too little or too large width), from the flow of data transmitted by the network and received on DCE receive line. The system also comprises new means for generating Lack of Receiver Timing (LRT) DCE internal signal (LRT is 'up' if there is a lack of a certain number of ASD square pulses within a given time), Block Error ASD (BEASD) DCE internal signal (BEASD is 'up' if so many ASD WIDTH ERROR pulses are counted within a given time), and Block Error Bipolar (BEBIP) DCE internal signal (BEBIP is 'up' if so many bipolar violations at the network interface, are detected within a given time). Finally, the system includes a logical decision process, which leads the DCE to automatically adjust its functional speed to the rate of data transmitted by the network and received on DCE receive line (step 710). The process consists in setting the DCE to the highest possible functional speed (step 701), and for that particular speed, checking all four of ACD (step 702), LRT (step 707), BEASD (step 708) and BEBIP (step 709) DCE internal signals; if one of the checkings is not satisfactory, setting the DCE to the next possible lower speed (step 704), or if all checkings are satisfactory, stopping the process as the DCE is ready to work (step 710).
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