公开(公告)号：DE69020685T2

公开(公告)日：1996-03-07

申请号：DE69020685

申请日：1990-10-22

Applicant: IBM

Inventor： KERWIN GREGORY JOHN ,  RAE JAMES WILSON

IPC: G11B20/10 ,  G11B20/18 ,  G11B27/36

Abstract: In a data storage device (eg: disk drive ) providing amplitude sampling data detection, the amplitude of an analog read back signal is sampled at data clock intervals. The resulting analog values are converted to digital equivalent values. The digital equivalent values are each compared to an expected digital values that is representative of the data that was originally recorded on the disk, to thereby generate a difference value. The resulting collection of difference values are magnitude segregated, and then stored in a plurality of registers, for later use in providing a histogram that is a measure of the disk drive's read error rate.

公开(公告)号：DE69020685D1

公开(公告)日：1995-08-10

申请号：DE69020685

申请日：1990-10-22

Applicant: IBM

Inventor： KERWIN GREGORY JOHN ,  RAE JAMES WILSON

IPC: G11B20/10 ,  G11B20/18 ,  G11B27/36

Abstract: In a data storage device (eg: disk drive ) providing amplitude sampling data detection, the amplitude of an analog read back signal is sampled at data clock intervals. The resulting analog values are converted to digital equivalent values. The digital equivalent values are each compared to an expected digital values that is representative of the data that was originally recorded on the disk, to thereby generate a difference value. The resulting collection of difference values are magnitude segregated, and then stored in a plurality of registers, for later use in providing a histogram that is a measure of the disk drive's read error rate.

公开(公告)号：DE68920692T2

公开(公告)日：1995-06-29

申请号：DE68920692

申请日：1989-10-16

Applicant: IBM

Inventor： CUNNINGHAM EARL ALBERT ,  PORTER TOWNSEND HENRY ,  RAE JAMES WILSON

IPC: G11B20/14 ,  H03L7/08 ,  H03L7/087 ,  H04L7/033 ,  H04L25/497

Abstract: Clocking of Class IV partial response coded binary data is provided by way of circuit means that includes two analog threshold detectors. One detector is responsive to the analog read signal's positive-going amplitude crossing a a preset positive threshold value. The other detector is responsive to the read signal's negative-going amplitude crossing a preset negative value. The time of occurrence of both detector crossing transitions is phase-compared to a clock signal, and a phase error signal is generated for each detector, if a phase error exists. The two phase error signals are integrated by the use of a loop filter. The integrated phase error signal is then used to adjust the phase of a clock signal generator. The output of the clock signal generator is used to accurately clock, and to enable accurate recover of, the binary data that was originally encoded and written in accordance with the Class IV partial responsive coding convention.

公开(公告)号：DE68920692D1

公开(公告)日：1995-03-02

申请号：DE68920692

申请日：1989-10-16

Applicant: IBM

Inventor： CUNNINGHAM EARL ALBERT ,  PORTER TOWNSEND HENRY ,  RAE JAMES WILSON

IPC: G11B20/14 ,  H03L7/08 ,  H03L7/087 ,  H04L7/033 ,  H04L25/497

Abstract: Clocking of Class IV partial response coded binary data is provided by way of circuit means that includes two analog threshold detectors. One detector is responsive to the analog read signal's positive-going amplitude crossing a a preset positive threshold value. The other detector is responsive to the read signal's negative-going amplitude crossing a preset negative value. The time of occurrence of both detector crossing transitions is phase-compared to a clock signal, and a phase error signal is generated for each detector, if a phase error exists. The two phase error signals are integrated by the use of a loop filter. The integrated phase error signal is then used to adjust the phase of a clock signal generator. The output of the clock signal generator is used to accurately clock, and to enable accurate recover of, the binary data that was originally encoded and written in accordance with the Class IV partial responsive coding convention.