公开(公告)号：DE1269393B

公开(公告)日：1968-05-30

申请号：DE1269393

申请日：1965-11-27

Applicant: IBM

Inventor： RAGLAND THOMAS

IPC: G06F9/22 ,  G06F9/26

Abstract: 1,074,903. Digital computers; misro-prigramming. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 13, 1965 [Dec. 4, 1964], No. 43346/65. Heading G4A. In a data processing system, a micro-programme read-only store 30, Fig. 3, is addressed through a register 32 which retains a variable length higher order portion of the address of the current instruction so that only the lower order content of the address of the next instruction need be contained in the present instruction where the addresses of succeeding instructions are sequential or differ by only a few low order bits. Data register 50 has 18 bits containing the current instruction, examples, Fig. 2 (not shown), which comprise: (a) 2-4 operation code bits fed by cable 42 to decoder 64; (b) 0-9 overlapping bits indicating the addresses of the data registers (19), Fig. 1 (not shown), used for the current instruction and fed by cable 76 to current address gates 74 and (c) 7-14 bits indicating either the whole, or at least 7, of the lower order bits of the next instruction fed by cable 54 to gates 52 and by a pair of cables 36, 37 to the low and high order portions of the address register 32. Operation code output lines such as 66, 68, 70 determine through OR circuits 08-014 and gates G(8-14), GR(8-14) which bits of the current address are retained and which bits are reset for the next instruction, being those bits remaining outside the current address field.

公开(公告)号：CA758259A

公开(公告)日：1967-05-02

申请号：CA758259D

Applicant: IBM

Inventor： RAGLAND THOMAS

公开(公告)号：DE1499722B1

公开(公告)日：1972-05-25

申请号：DE1499722

申请日：1966-10-11

Applicant: IBM DEUTSCHLAND

Inventor： HOWARD OTTAWAY GERALD ,  PAINKE HELMUT ,  RAGLAND THOMAS ,  SCHELER TITUS ,  WILL HELMUT ,  VAUGHN WRIGHT WILLIAM

IPC: G06F9/26 ,  G06F9/20

Abstract: 1,107,486. Microprogramming. INTERNATIONAL BUSINESS MACHINES CORPORATION. 25 Aug., 1966 [22 Oct., 1965], No. 38140/66. Heading G4A. Bits from a stored word are subjected to a variable logical operation to get the address of the next word. An address applied to a computer microprogramme read-only store controls three decoders. The first two decoders select a word location in the store and the third decoder selects and passes to a register one of three portions of the word as the next micro-instruction. Either of two of the portions fills the register but the third leaves a part of the register unchanged. The next store address is obtained from sections of said register, said " part " of the register feeding the second decoder, another part feeding the third decoder, and a third part being applied to the first decoder via a " use " circuit which either passes the third part unchanged, or AND's or OR's or EXCL-OR's the bits of the third part with corresponding bits from one of a number of working registers in the computer. What the " use " circuit does to the third part is controlled by other bits from the current microinstruction.

公开(公告)号：CA807311A

公开(公告)日：1969-02-25

申请号：CA807311D

Applicant: IBM

Inventor： WRIGHT WILLIAM V ,  WILL HELMUT ,  OTTOWAY GERALD H ,  RAGLAND THOMAS ,  SCHELER TITUS ,  PAINKE HELMUT