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    1.
    发明专利
    未知

    公开(公告)号：DE1499727A1

    公开(公告)日：1972-04-13

    申请号：DE1499727

    申请日：1966-10-12

    Applicant: IBM DEUTSCHLAND INTERNAT BUERO

    Inventor： HOWARD OTTAWAY GERALS ,  PAINKE HELMUT ,  SCHELER TITUS ,  WILL HELMUT ,  VAUGHN WRIGHT WILLIAM

    IPC: G06F9/26 ,  G06F9/00

    Abstract: 1,105,394. Data storage: micro-programme control arrangements. INTERNATIONAL BUSINESS MACHINES CORPORATION. 31 Aug., 1966 [22 Oct., 1965], No. 38738/66. Heading G4A. Certain of the data in a storage register associated with a digital electric data store can be maintained from one storage access cycle to another, means being provided responsive to the state of certain other data positions to select which bytes of a next-to-be addressed word in the store are to be moved into the storage register. In digital electric data-storage apparatus wherein each storage word includes as a portion thereof at least a portion of the address of the next succeeding storage word, storage space is saved due to the fact that when dealing with a sequence of storage words located within adjacent areas of the store the common high order address bits are saved from one storage access cycle to the next. The invention has particular application to micro-programme control using read-only stores. In the arrangement shown (Fig. 1), a read only store (ROS) 22 stores 60-bit storage words which are divided into three instruction words A, B, C of 16, 22 and 22 bits each respectively. One only of these words A, B, or C is transferred during any storage access cycle into ROS register 24 the particular one chosen depending on the configuration of bits 16 and 17 in ROS address register (ROSAR) 28, these bits, originating from the previous micro-instruction, being decoded by word select decoder WD SEL DEC 26 (shown in detail in Fig. 2, not shown). In those cases where word A is selected, bits 10 to 15 of ROS REG 24 remain undisturbed to form the high order part of the next address. USE circuit 34 allows optional (programmed) modification of address bits 18-21 of ROS REG 24 before these bits are applied to ROSAR 29. Bits 1-9, forming the order part of the instruction word, are applied to decode circuits 38 in conventional manner. ROS REG 24 is shown in more detail in Fig. 2 (not shown).

    2.
    发明专利
    未知

    公开(公告)号：DE1499722B1

    公开(公告)日：1972-05-25

    申请号：DE1499722

    申请日：1966-10-11

    Applicant: IBM DEUTSCHLAND

    Inventor： HOWARD OTTAWAY GERALD ,  PAINKE HELMUT ,  RAGLAND THOMAS ,  SCHELER TITUS ,  WILL HELMUT ,  VAUGHN WRIGHT WILLIAM

    IPC: G06F9/26 ,  G06F9/20

    Abstract: 1,107,486. Microprogramming. INTERNATIONAL BUSINESS MACHINES CORPORATION. 25 Aug., 1966 [22 Oct., 1965], No. 38140/66. Heading G4A. Bits from a stored word are subjected to a variable logical operation to get the address of the next word. An address applied to a computer microprogramme read-only store controls three decoders. The first two decoders select a word location in the store and the third decoder selects and passes to a register one of three portions of the word as the next micro-instruction. Either of two of the portions fills the register but the third leaves a part of the register unchanged. The next store address is obtained from sections of said register, said " part " of the register feeding the second decoder, another part feeding the third decoder, and a third part being applied to the first decoder via a " use " circuit which either passes the third part unchanged, or AND's or OR's or EXCL-OR's the bits of the third part with corresponding bits from one of a number of working registers in the computer. What the " use " circuit does to the third part is controlled by other bits from the current microinstruction.

    Data storage apparatus
    7.
    发明专利
    Data storage apparatus 未知

    公开(公告)号：GB1078383A

    公开(公告)日：1967-08-09

    申请号：GB1118966

    申请日：1966-03-15

    Applicant: IBM

    Inventor： SCHELER TITUS ,  GENG ROLAND ,  KUENDEL GERHARD ,  HODGES PAUL ,  UTLEY BRIAN GEORGE

    IPC: G11C21/00

    Abstract: 1,078,383. Data storage. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 15, 1966 [March 26, 1965], No. 11189/66. Heading G4C. A recirculating store has (n+1) storage positions to enable a set of n characters stored therein to be read in the reverse order, there being means for reading out every n character times from a particular storage position. Referring to Fig. 1 (not shown), a delay line (LSp) has outputs (N, L) n and (n+ 1) character positions from the input (E), either being connectible to feed the input (E) for recirculation. Reversal is achieved by using the (n+1) output (L) for recirculation and gating (U) a character from the n output every n character times, using a counter (ZZ). Leading zeros may be suppressed by changing the output used for recirculation under control of comparison of the two outputs (N, L). A magnetic drum or disc may replace the delay line.

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