公开(公告)号：JP2000357749A

公开(公告)日：2000-12-26

申请号：JP2000160921

申请日：2000-05-30

Applicant: IBM

Inventor： MANDELMAN JACK ALLAN ,  BRONER GERI B ,  RAMACHANDRA DEIBAKARUNI

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a double work function doping and a borderless array diffusion contact. SOLUTION: This method includes steps for forming a semiconductor substrate 5, a gate insulator 10, conductors 61, 12 on the gate insulator, an insulation cap on the conductors, and an insulation spacer 92 on part of the sidewall of the conductors and of the insulation cap. This method also includes a step for doping a part of the semiconductor substrate and of the conductors with a first conductive dopant and the other part with a second conductive dopant. The conductors are annealed, to allow the first and the second conductive dopants to spread crossing into into each conductor.

公开(公告)号：JP2004088100A

公开(公告)日：2004-03-18

申请号：JP2003287161

申请日：2003-08-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KHAN BABAR A ,  RADENS CARL J ,  RAMACHANDRA DEIBAKARUNI

IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L27/10891 ,  H01L27/0207 ,  H01L27/10864

Abstract: PROBLEM TO BE SOLVED: To provide the structure of a built-in DRAM with a vertical device array and a bordered bit line contact, and a manufacturing method of the built-in DRAM.
SOLUTION: In an integrated circuit including a dynamic random access memory (DRAM), a DRAM cell has a storage capacitor in a deep trench, a transistor which has channels extending along side walls of the deep trench and a gate conductor in the deep trench, and a word line which makes contact with the gate conductor from above. The word line has a center line deviating from the center line of the gate conductor. The DRAM cell also has active regions extending from channels of the transistor and a bit line contact to the active regions, which are bordered by insulation spacers on side walls of the word line.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2010157704A

公开(公告)日：2010-07-15

申请号：JP2009271765

申请日：2009-11-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GAMBINO JEFFREY P ,  PETRARCA KEVIN S ,  FAROOQ MUKTA G ,  RAMACHANDRA DEIBAKARUNI

IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/866

CPC classification number: H01L28/60 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a metal-insulator-metal capacitor having improved manufacturing possibility, and to provide a method for fabricating the same. SOLUTION: A semiconductor structure including the vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor field effect transistor located and formed over an isolation region located over a semiconductor substrate. The dummy metal oxide field effect transistor may be formed simultaneously with a metal oxide semiconductor field effect transistor located over a semiconductor substrate that includes the isolation region. The metal-insulator-metal capacitor uses a gate as a capacitor plate, a uniform thickness gate spacer as a gate dielectric and a contact via as another capacitor plate. The uniform thickness gate spacer may include a conductor layer for enhanced capacitance. A mirrored metal-insulator-metal capacitor structure that uses a single contact via may also be used for enhanced capacitance. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供具有改进的制造可能性的金属 - 绝缘体 - 金属电容器，并提供其制造方法。 解决方案：包括垂直金属 - 绝缘体 - 金属电容器的半导体结构以及包括垂直金属 - 绝缘体 - 金属电容器的半导体结构的制造方法，每个都使用来自虚设金属氧化物半导体场效应晶体管的结构部件 并且形成在位于半导体衬底上方的隔离区域上。 虚拟金属氧化物场效应晶体管可以与位于包括隔离区域的半导体衬底之上的金属氧化物半导体场效应晶体管同时形成。 金属 - 绝缘体 - 金属电容器使用栅极作为电容器板，均匀厚度的栅极间隔物作为栅极电介质和作为另一个电容器板的接触通孔。 均匀厚度的栅极间隔物可以包括用于增强电容的导体层。 使用单个接触通孔的镜像金属 - 绝缘体 - 金属电容器结构也可用于增强电容。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2006253684A

公开(公告)日：2006-09-21

申请号：JP2006061418

申请日：2006-03-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHENG KANGGUO ,  RAMACHANDRA DEIBAKARUNI ,  HO HERBERT L ,  KARL J REEDENSU

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/76 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/08 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L27/10864 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

Abstract: PROBLEM TO BE SOLVED: To provides a structure including a trench capacitor array at least part of which is arranged under an embedded oxide layer of an SOI substrate.
SOLUTION: Each trench capacitor shares a common unitary embedded capacitor plate including at least part of a first unitary semiconductor region arranged under an embedded oxide layer. An upper boundary of the embedded capacitor plate defines a plane extending laterally over the whole trench capacitor array parallel to the major surface of a substrate. In a particular embodiment starting at an SOI substrate or a bulk substrate, the trench array and contact holes are formed at the same time such that the contact holes extend in the same depth as that of the trenches. Preferably, the width of the contact hole is substantially large compared with that of the trench, thereby forming conductive contact vias at the same time by processing used for forming a trench capacitor extending along the wall of the trench.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种包括沟槽电容器阵列的结构，其至少一部分布置在SOI衬底的嵌入式氧化物层的下方。 解决方案：每个沟槽电容器共享共同的单一嵌入式电容器板，其包括布置在嵌入式氧化物层下方的第一单元半导体区域的至少一部分。 嵌入式电容器板的上边界限定了平行于衬底的主表面的整个沟槽电容器阵列上横向延伸的平面。 在从SOI衬底或体衬底开始的特定实施例中，沟槽阵列和接触孔同时形成，使得接触孔在与沟槽的深度相同的深度上延伸。 优选地，接触孔的宽度与沟槽的宽度相比基本上大，由此通过用于形成沿沟槽壁延伸的沟槽电容器的处理同时形成导电接触孔。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004274063A

公开(公告)日：2004-09-30

申请号：JP2004064681

申请日：2004-03-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YANG HAINING ,  RAMACHANDRA DEIBAKARUNI

IPC: H01L27/10 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/1087 ,  H01L27/10841 ,  H01L29/66181

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a single bit line contact on a vertical transistor of a DRAM/e-DRAM device using a line forming master mask.
SOLUTION: By forming a patterning mask on the device with the line forming master mask, the part of the top surface of a gate electrode 100 is exposed on the top surface of a substrate. A divot reaching in the gate electrode alongside with a side wall spacer 300 juxtaposed with a source region 130 is etched, and filled with a dielectric material. A word line WL having a silicon nitride cap 220 is formed to be contacted with a gate electrode 100. An etching resistant conformal liner 230 is formed, and an ILD layer and a glass layer are formed. A bit line contact mask is formed to be patterned with the line forming master mask. A via hole BCV is etched to be juxtaposed with the side wall spacer 300 and reach to the source region 130, and the bit line contact is formed.
COPYRIGHT: (C)2004,JPO&NCIPI