公开(公告)号：DE3271063D1

公开(公告)日：1986-06-12

申请号：DE3271063

申请日：1982-12-07

Applicant: IBM

Inventor： LOSQ JACQUES JEAN ,  RAO GURURAJ SESHAGIRI ,  SACHAR HOWARD EDWARD

IPC: G06F9/38

Abstract: Instruction prefetching data processing apparatus is adapted for predicting the outcome of a conditional branch instruction based on the previous performance of the branch, rather than on the instruction fields. The prediction of the outcome of a conditional branch instruction is performed utilizing a decode-time history table (6) that records the history of the outcome of the branch at a given memory location. The predictor attempts to guess only the outcome of a conditional branch instruction, but not its target address and can only be used to guess the branch outcomes at decode time when the target address is available. The table is accessed using the memory address of the branch instruction itself or some portions thereof. The table records the history of the outcomes of the branch at this memory location up to the congruence of the table size. A combinational circuit (18) determines the guess (taken or not taken) from the branch history as provided by the table.