INSTRUCTION PREFETCHING DATA PROCESSING APPARATUS INCLUDING A CONDITIONAL BRANCH INSTRUCTION PREDICTOR

    公开(公告)号:DE3271063D1

    公开(公告)日:1986-06-12

    申请号:DE3271063

    申请日:1982-12-07

    Applicant: IBM

    Abstract: Instruction prefetching data processing apparatus is adapted for predicting the outcome of a conditional branch instruction based on the previous performance of the branch, rather than on the instruction fields. The prediction of the outcome of a conditional branch instruction is performed utilizing a decode-time history table (6) that records the history of the outcome of the branch at a given memory location. The predictor attempts to guess only the outcome of a conditional branch instruction, but not its target address and can only be used to guess the branch outcomes at decode time when the target address is available. The table is accessed using the memory address of the branch instruction itself or some portions thereof. The table records the history of the outcomes of the branch at this memory location up to the congruence of the table size. A combinational circuit (18) determines the guess (taken or not taken) from the branch history as provided by the table.

    2.
    发明专利
    未知

    公开(公告)号:DE3481233D1

    公开(公告)日:1990-03-08

    申请号:DE3481233

    申请日:1984-02-29

    Applicant: IBM

    Abstract: A pair of inherently sequential instructions, having an instruction dependency of the type in which the subsequent instruction requires as an input operand the result of the earlier instruction execution, can nevertheless be simultaneously executed by two data flow facilities (primary and secondary) under control of a control unit, without the requirement that both data flow facilities be fully equipped for all instructions. … The secondary data flow facility of this invention is generally less massive and less sophisticated than the primary data flow facility but is more sophisticated in a critical organ, the adder. The adder in the secondary data flow facility has one additional operand capability. The three-input adder of the secondary data flow facility thus is capable of replicating internally a result of the two-input adder of the primary data flow facility. Using this replicated primary adder "result", together with the additional operand capability, the secondary data flow facility three- input adder executes the dependent subsequent instruction of the pair simultaneously with the earlier instruction execution by the primary data flow facility.

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