公开(公告)号：GB2581053A

公开(公告)日：2020-08-05

申请号：GB202005185

申请日：2017-12-19

Applicant: IBM

Inventor： SAMI ROSENBLATT ,  RASIT TOPALOGU ,  JARED BARNEY HERTZBERG ,  WERNER A RAUSCH

IPC: H01L39/22 ,  G06N10/00 ,  H01G4/005 ,  H01L27/18 ,  H01L29/24

Abstract: A vertical q-capacitor (202, 302, 700, 1100, 1400, 1800) includes a trench (304, 502, 902, 1202, 1204, 1602) in a substrate (400) through a layer (602, 1302, 1304) of superconducting material (402). A superconductor is deposited in the trench (304, 502, 902, 1202, 1204, 1602) forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench (304, 502, 902, 1202, 1204, 1602). The first and second surfaces are substantially parallel, and the third surface in the trench (304, 502, 902, 1202, 1204, 1602) separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor (202, 302, 700, 1100, 1400, 1800) that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.

公开(公告)号：GB2581053B

公开(公告)日：2021-11-03

申请号：GB202005185

申请日：2017-12-19

Applicant: IBM

Inventor： SAMI ROSENBLATT ,  RASIT TOPALOGU ,  JARED BARNEY HERTZBERG ,  WERNER A RAUSCH

IPC: H01L39/22 ,  G06N10/00 ,  H01G4/005 ,  H01L27/18 ,  H01L29/24

Abstract: A vertical q-capacitor includes a trench in a substrate through a layer of superconducting material. A superconductor is deposited in the trench forming a first film on a first surface, a second film on a second surface, and a third film of the superconductor on a third surface of the trench. The first and second surfaces are substantially parallel, and the third surface in the trench separates the first and second surfaces. A dielectric is exposed below the third film by etching. A first coupling is formed between the first film and a first contact, and a second coupling is formed between the second film and a second contact in a superconducting quantum logic circuit. The first and second couplings cause the first and second films to operate as the vertical q-capacitor that maintains integrity of data in the superconducting quantum logic circuit within a threshold level.