公开(公告)号：GB2374984B

公开(公告)日：2004-10-06

申请号：GB0110072

申请日：2001-04-25

Applicant: IBM

Inventor： OGGIONI STEFANO ,  RAVANELLI ROBERTO

IPC: H01L23/498 ,  H01L23/66 ,  H05K1/02 ,  H05K1/11 ,  H05K3/42

Abstract: A multi-layered circuitized substrate for high-frequency applications. Conductive via-holes extend between two non-adjacent conductive layers for transmitting high-frequency signals therebetween. For each via-hole, shielding rings connectable to a reference voltage are provided, each ring formed in a corresponding intermediate conductive layer between the two non-adjacent conductive layers. The rings define a shielding coaxial structure for the via-hole. Preferably, the intermediate conductive layers are spaced apart from the via-hole, and particularly from respective lands at the ends thereof, in order to reduce stray capacitance associated with the via-hole without losing the shielding effect provided by the rings.

公开(公告)号：GB2374984A

公开(公告)日：2002-10-30

申请号：GB0110072

申请日：2001-04-25

Applicant: IBM

Inventor： OGGIONI STEFANO ,  RAVANELLI ROBERTO

IPC: H01L23/498 ,  H01L23/66 ,  H05K1/02 ,  H05K1/11 ,  H05K3/42

Abstract: A chip carrier (120), or an equivalent circuitised substrate, for high-frequency applications with a multi-layer structure, has via-holes (145) which extend between two non-adjacent conductive layers (210a,210f) for transmitting high-frequency signals. The chip carrier includes, for each via-hole, shielding rings (230b-230e) connectable to a reference voltage; each ring is formed in a corresponding intermediate conductive layer (210b-210e) between the two non-adjacent conductive layers, and is closed around the via-hole. The rings define a shielding coaxial structure for the via-hole. Preferably, the intermediate conductive layers are spaced apart from the via-hole, and particularly from respective lands (125,150), in order to reduce the capacitance of stray capacitors associated with the via-hole (without losing the shielding effect provided by the rings).

公开(公告)号：GB2368454B

公开(公告)日：2005-04-06

申请号：GB0025985

申请日：2000-10-24

Applicant: IBM

Inventor： OGGIONI STEFANO ,  RAVANELLI ROBERTO

IPC: H01L23/498 ,  H01L23/552 ,  H01L23/66

Abstract: An electronic package is provided. The electronic package includes a chip carrier having a first conductive layer which includes at least one signal track and at least one contact area, the contact area being electrically connected to the signal track and adapted for transmitting a high-frequency signal. The chip carrier further includes a reference structure having at least two conductive layers such that the signal track is electrically shielded by the reference structure. A semiconductor chip is positioned on the chip carrier and includes at least one terminal electrically interconnected to the at least one contact area.

公开(公告)号：GB2368454A

公开(公告)日：2002-05-01

申请号：GB0025985

申请日：2000-10-24

Applicant: IBM

Inventor： OGGIONI STEFANO ,  RAVANELLI ROBERTO

IPC: H01L23/498 ,  H01L23/552 ,  H01L23/66

Abstract: A chip carrier (110) for a high-frequency electronic device (100) has a circuitised substrate (115) with a plurality of conductive layers (210a-210d) insulated from each other. The conductive layers are arranged in a sequence. A first one of the conductive layers (210a) has a plurality of signal tracks (104s) each one ending with a contact area (145s) for transmitting a high-frequency signal. A reference structure (215g,225g,140ch,140cl) is connectable to a reference voltage for shielding the signal tracks. The reference structure includes at least one reference track (215g) formed in a second one of the conductive layers (210b) adjacent to the first conductive layer and at least one further reference track (225g) is formed in one of the conductive layers (210d) different from the first and second conductive layer. A portion of each signal track excluding the contact area is superimposed in plan view to a corresponding reference track and the contact area of each signal track is superimposed in plan view to a corresponding further reference track without interposition of any other of the conductive layers (210a-210c).