公开(公告)号：EP0206462A2

公开(公告)日：1986-12-30

申请号：EP86302860

申请日：1986-04-16

Applicant: IBM

Inventor： LING DANIEL TAJEN ,  OKLOBDZIJA VOJIN G ,  RAVER NORMAN

IPC: H03K19/096 ,  H03K17/687 ,  H03K19/173

CPC classification number: H03K19/1738

Abstract: A precharge circuit for a cascode voltage switch n which at the beginning of the precharge phase the output state is memorised and the output is isolated from the precharging points. Both the positive and negative ends of the discharge paths are precharged with the gates of the switches in all paths held in :heir memorised states. Towards the end of precharging, the output is reconnected to the normal precharging point so that it goes low. Then the positive and negative precharging points are reconnected for their evaluation configuration.

公开(公告)号：JPH0585090B2

公开(公告)日：1993-12-06

申请号：JP4205786

申请日：1986-02-28

Applicant: IBM

Inventor： LING DANIEL TAJEN ,  OKLOBDZIJA VOJIN G ,  RAVER NORMAN

IPC: H03K19/096 ,  H03K17/687 ,  H03K19/173

公开(公告)号：JPS61247122A

公开(公告)日：1986-11-04

申请号：JP4205786

申请日：1986-02-28

Applicant: IBM

Inventor： LING DANIEL TAJEN ,  OKLOBDZIJA VOJIN G ,  RAVER NORMAN

IPC: H03K19/096 ,  H03K17/687 ,  H03K19/173

公开(公告)号：CA721421A

公开(公告)日：1965-11-09

申请号：CA721421D

Applicant: IBM

Inventor： HANAN MAURICE ,  PALERMO FRANK P ,  RAVER NORMAN ,  SCHAY GEZA

公开(公告)号：DE69009165D1

公开(公告)日：1994-06-30

申请号：DE69009165

申请日：1990-09-19

Applicant: IBM

Inventor： JACKSON KENNETHH PAUL ,  RAVER NORMAN

IPC: H01L25/00 ,  G02B6/42 ,  H01S5/00 ,  H05K1/02

Abstract: Electrical circuit including a first array (22) and a second array (16) of electrical components mounted on a circuit board having an electrically conductive cladding (20), comprising a system for interconnecting the components of the first array to the components of the second array with parallel signal channels. In each of the channels, there is one electrically conductive strip (48) formed within the cladding (20) and providing for a path of current from a component of the second array to a component of the first array. A second conductive path is provided for conducting current from the first array to the second array. The conductive strip forms therewith a portion of a loop which generates a magnetic field in the presence of currents flowing through the two paths. There is magnetic coupling between the paths of one channel to the paths of the other channel, the magnetic coupling provided by the wire loops having a positive coefficient of mutual inductance while the coupling from loops lying in a plane parallel to the padding is characterized by a mutual inductance of negative coupling coefficient. The positive and the negative mutual inductances tend to cancel for reduction of crosstalk among the channels.

公开(公告)号：DE69009165T2

公开(公告)日：1994-12-01

申请号：DE69009165

申请日：1990-09-19

Applicant: IBM

Inventor： JACKSON KENNETHH PAUL ,  RAVER NORMAN

IPC: H01L25/00 ,  G02B6/42 ,  H01S5/00 ,  H05K1/02

Abstract: Electrical circuit including a first array (22) and a second array (16) of electrical components mounted on a circuit board having an electrically conductive cladding (20), comprising a system for interconnecting the components of the first array to the components of the second array with parallel signal channels. In each of the channels, there is one electrically conductive strip (48) formed within the cladding (20) and providing for a path of current from a component of the second array to a component of the first array. A second conductive path is provided for conducting current from the first array to the second array. The conductive strip forms therewith a portion of a loop which generates a magnetic field in the presence of currents flowing through the two paths. There is magnetic coupling between the paths of one channel to the paths of the other channel, the magnetic coupling provided by the wire loops having a positive coefficient of mutual inductance while the coupling from loops lying in a plane parallel to the padding is characterized by a mutual inductance of negative coupling coefficient. The positive and the negative mutual inductances tend to cancel for reduction of crosstalk among the channels.

公开(公告)号：DE3584737D1

公开(公告)日：1992-01-09

申请号：DE3584737

申请日：1985-05-21

Applicant: IBM

Inventor： RAVER NORMAN

IPC: H03K5/13 ,  H03K5/00 ,  H03K5/04

Abstract: A circuit for generating accurate timing pulses which includes a timer means (10), a reference and feedback amplifier means (12), a feedback difference amplifier means (14), a difference amplifier means (16) and a pulse shaper means (18). The timer means (10) includes a constant current source which is triggered on by the input waveform signal and produces current i c . Reference and feedback amplifier means generates a voltage V ref which is proportional to current i c . Thus, if i c is too high or too low, V ref will represent the error value. The d.c. reference signal V ref, is applied to the feedback difference amplifier means (14) which is a typical dynamic detector circuit. Feedback difference amplifier circuit is triggered and changes state when the voltage of the constant current timing circuit (which is proportional to i o ) equals the reference voltage V,.,'.The output signal from feedback difference amplifier means (14) is applied to the straightforward difference amplifier means (16) for further amplication. The amplified output voltage signal is then applied to the pulse shaper circuit means (18) along with the original input signal such that the timing of the input signal is adjusted in accordance with the signal from the difference amplifier to produce an output timing pulse.

公开(公告)号：DE3682121D1

公开(公告)日：1991-11-28

申请号：DE3682121

申请日：1986-04-16

Applicant: IBM

Inventor： LING DANIEL TAJEN ,  OKLOBDZIJA VOJIN G ,  RAVER NORMAN

IPC: H03K19/096 ,  H03K17/687 ,  H03K19/173

Abstract: A precharge circuit for a cascode voltage switch n which at the beginning of the precharge phase the output state is memorised and the output is isolated from the precharging points. Both the positive and negative ends of the discharge paths are precharged with the gates of the switches in all paths held in :heir memorised states. Towards the end of precharging, the output is reconnected to the normal precharging point so that it goes low. Then the positive and negative precharging points are reconnected for their evaluation configuration.

公开(公告)号：DE3582086D1

公开(公告)日：1991-04-18

申请号：DE3582086

申请日：1985-05-21

Applicant: IBM

Inventor： RAVER NORMAN

IPC: H03K4/94 ,  H03K6/04 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K5/02

Abstract: (D An off-chip driver (OCD) circuit is described including a first output device (10) and a second output device (12) having a common output connection (14) wherein a rising (1 bit) or falling (0 bit) signal is applied through an input circuit (8) to the output devices.The output signal which appears at the common output connection will exhibit a rise time and a fall time corresponding to the rise and fall of the input signal.A first monitoring device (18) is connected to the output signal to monitor the rise time of the output signal and a second monitoring device (20) is connected to the output signal to monitor the fall time of the output signal.A ramp generator (22) is provided which generates a reference signal which also includes a rise time and a fall time.The two monitor circuits (18, 20) compare the rise and fall times of the output signal with the reference rise time and reference fall time to produce a feedback signal to control the rise and fall times of the output signal in accordance with the reference signal.

公开(公告)号：DE1474039A1

公开(公告)日：1968-12-12

申请号：DE1474039

申请日：1964-04-08

Applicant: IBM

Inventor： HANAN MAURICE ,  PANTELEONE PALERMO FRANK ,  RAVER NORMAN ,  HEIGHTS YORKTOWN ,  SCHAY GEZA

IPC: G06F17/30

Abstract: 1,030,253. Addressing memories; code conversions. INTERNATIONAL BUSINESS MACHINES CORPORATION. March 19, 1964 [April 12, 1963], No. 11582/64. Headings G4A and G4C. In a data storage apparatus, a set of keys is mapped on to a smaller set of addresses by means for performing an algebraic transformation on each of said keys to provide a respective address, whereby keys separated by a Hamming distance of less than a predetermined amount are provided with different addresses. Referring to Fig. 1, a key K=(k0, k1, k2 ... k29) shifted into register 12 is converted into an address A=(a0, a1 . . . a4). Each element ki, ai is represented as six bits in parallel (and is an element of a Galois field-see Table I of the Specification). If the key K and address A are represented as polynomials K(X) and A(X) (the elements ki and ai being the coefficients of the terms thereof) the conversion may be represented where G(X) is a suitable (e.g. Bose-Chaudhuri) generator polynomial and Q(X) a quotient. The elements ki of the key K are shifted in turn into a chain of flip-flop sets 20-1 to 20-5, each set comprising six flip-flops. An element shifted out of set 20-5 goes to each of multiplier units 40-1 to 40-5, each of which comprises singlebit modulo-2 adders (i.e. exclusive-or gates) so connected that the output of the multiplier unit equals the input multiplied by one digit (coefficient) of the generator polynomial G(X). Each of the six bits of the output of each multiplier unit 40-1 to 40-5 is added modulo-2 to the corresponding bit of the next element ki approaching a corresponding flip-flop set 20-1 to 20-5, at a corresponding set of six modulo-2 adder units 32-1 or &c., the result of the addition entering the flip-flop set 20-1 or &c. When the last element k0 is shifted out of register 12, a counter and delay unit 15-2, after a short delay, enables a random-access memory 16 to respond to the contents of the fllip-flop sets 20-1 to 20-5, these being the required address. The multiplier units 40-1 to 40-5 are different from each other and have internal structures simulating the multiplicand, but as a modification each may be the same, comprising AND-gates and modulo-2 adder units and being supplied with the multiplicand over a set of six wires from a storage register. The key to address conversion may equivalently be represented by a suitable matrix [tij], thus: the matrix elements tij (each being six bits in parallel) being passed in turn to a single multiplier via a set of six delay line stores (one per bit position) and a six-bit register. The multiplier is also supplied with the key elements kj in turn from a shift register. When a given key element kj is presented it is multiplied by the appropriate five tij in turn, the answers being sent to five six-bit accumulators respectively. At the end, each accumulator is thus left storing one of the address elements ai (Figs. 8, 9, not shown).