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    Method of precharging and precharge circuit for dynamic cascode voltage switch logic.
    1.
    发明公开
    Method of precharging and precharge circuit for dynamic cascode voltage switch logic. 失效
    方法和Schattungsanordnung预充电动态共源共栅逻辑电路。

    公开(公告)号：EP0206462A2

    公开(公告)日：1986-12-30

    申请号：EP86302860

    申请日：1986-04-16

    Applicant: IBM

    Inventor： LING DANIEL TAJEN ,  OKLOBDZIJA VOJIN G ,  RAVER NORMAN

    IPC: H03K19/096 ,  H03K17/687 ,  H03K19/173

    CPC classification number: H03K19/1738

    Abstract: A precharge circuit for a cascode voltage switch n which at the beginning of the precharge phase the output state is memorised and the output is isolated from the precharging points. Both the positive and negative ends of the discharge paths are precharged with the gates of the switches in all paths held in :heir memorised states. Towards the end of precharging, the output is reconnected to the normal precharging point so that it goes low. Then the positive and negative precharging points are reconnected for their evaluation configuration.

    REGISTER SELECTION MECHANISM AND ORGANIZATION OF AN INSTRUCTION PREFETCH BUFFER
    5.
    发明专利
    REGISTER SELECTION MECHANISM AND ORGANIZATION OF AN INSTRUCTION PREFETCH BUFFER 未知

    公开(公告)号：CA1233270A

    公开(公告)日：1988-02-23

    申请号：CA490347

    申请日：1985-09-10

    Applicant: IBM

    Inventor： OKLOBDZIJA VOJIN G

    IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G11C5/02 ,  G06F12/04 ,  G11C7/00

    Abstract: A register selection mechanism is disclosed for an instruction prefetch buffer which allows instructions having different lengths to be accessed on the instruction boundaries. The instruction prefetch buffer comprises a one-port-write, two-port-read array (10). Address generation and control logic (16) is responsive to a read pointer (15) for controlling access to odd and even addresses in the array. Additional logic may be provided to provide an indication that the instruction prefetch buffer is empty.

    7.
    发明专利
    未知

    公开(公告)号：DE3682121D1

    公开(公告)日：1991-11-28

    申请号：DE3682121

    申请日：1986-04-16

    Applicant: IBM

    Inventor： LING DANIEL TAJEN ,  OKLOBDZIJA VOJIN G ,  RAVER NORMAN

    IPC: H03K19/096 ,  H03K17/687 ,  H03K19/173

    Abstract: A precharge circuit for a cascode voltage switch n which at the beginning of the precharge phase the output state is memorised and the output is isolated from the precharging points. Both the positive and negative ends of the discharge paths are precharged with the gates of the switches in all paths held in :heir memorised states. Towards the end of precharging, the output is reconnected to the normal precharging point so that it goes low. Then the positive and negative precharging points are reconnected for their evaluation configuration.

    INSTRUCTION PREFETCH BUFFER CONTROL
    8.
    发明专利
    INSTRUCTION PREFETCH BUFFER CONTROL 未知

    公开(公告)号：CA1242282A

    公开(公告)日：1988-09-20

    申请号：CA502803

    申请日：1986-02-26

    Applicant: IBM

    Inventor： OKLOBDZIJA VOJIN G

    IPC: G06F9/38

    Abstract: An instruction prefetch buffer control (20) is provided for an instruction prefetch buffer array (10) which stores the code for a number of instructions that have already been executed as well as the code for a number of instructions yet to be executed. The instruction prefetch buffer control includes a register (201) for storing an instruction fetch pointer, this pointer being supplied to the buffer array (10) as a write pointer which points to the location in the array where a new word is to be written from main memory. A second register (205) stores an instruction execution pointer which is supplied to the buffer array (10) as a read pointer. A first adder (203) increments the first register to increment the instruction fetch pointer for sequential instructions and calculates a new instruction fetch pointer for branch instructions. A second adder (215) increments the second register to increment the instruction execution pointer for sequential instructions and calculates a new instruction execution pointer for branch instructions. Incrementing of the second register is variable depending on the length of the instruction. A third adder (221) is responsive to the output of the first adder and a branch target address to calculate whether the target instruction is contained in the array (10) and, if it is, causes the new- instruction execution pointer calculated by the second adder (215) to be loaded into the second register (205).

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