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公开(公告)号：JPH11272464A
公开(公告)日：1999-10-08
申请号：JP2597099
申请日：1999-02-03
Inventor： RAY DAVID SCOTT , WILLIAMSON BARRY DUANE , TUNG SHIH-HSIUNG STEPHEN
CPC classification number: G06F9/30043 , G06F9/3824
Abstract: PROBLEM TO BE SOLVED: To realize the speculative execution of a non-array cache access instruction by preventing the non-array cache access instruction from being dispatched much more until head/last instructions are completed.
SOLUTION: When an instruction to be loaded is dispatched, access to a cache 206 is required for two times. A logic circuit in a data unit 204 recognizes that data requiring the instruction is not arrayed, the two primitive instructions of an instruction marked as a head and an instruction marked as the last, which are required for obtaining data, are generated. The data unit 204 asserts one bit to a non-array/busy latch 208. Thus, the dispatch unit is stopped to issue the non-array instructions much more. The other instruction of an array loading instruction can be dispatched and it can be processed by a circuit 200.
COPYRIGHT: (C)1999,JPOAbstract translation: 要解决的问题：通过防止非阵列高速缓存访问指令被调度得更多，直到头/最后指令完成来实现非阵列高速缓存访问指令的推测执行。 解决方案：当调度要加载的指令时，需要访问高速缓存206两次。 数据单元204中的逻辑电路识别出没有排列需要指令的数据，生成标记为头的指令的两个原语指令和标记为最后的指令，这是获得数据所需的指令。 数据单元204向非阵列/忙锁存器208断言一位。因此，停止发送单元以发出非阵列指令。 可以调度阵列加载指令的另一指令，并且可以由电路200进行处理。
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公开(公告)号：JPH11272466A
公开(公告)日：1999-10-08
申请号：JP2585799
申请日：1999-02-03
Inventor： TUNG SHIH-HSIUNG STEPHEN , RAY DAVID SCOTT , CHIAROT KEVIN ARTHUR , WILLIAMSON BARRY DUANE
CPC classification number: G06F9/3834 , G06F12/0859
Abstract: PROBLEM TO BE SOLVED: To eliminate a loading queue and to cancel an instruction which is possibly terminated through the use of illegal data by comparing address information in a misqueue table with an address which is possibly changed.
SOLUTION: Whenever an instruction is dispatched, an item is generated in a misqueue table. When the instruction is hit in a data cache 206, the item of the instruction is removed from the misqueue table at a next cycle. When the instruction is missed in the data cache 206, a real address, a valid address and other information are left in the misqueue table. A processor always scans address information on the item in the misqueue table and tries access to the cache at a valid address stored in the misqueue table at respective cycles. Data can be obtained in the cache 206 on the respective items in the misqueue table and it is transferred to a formatter 210.
COPYRIGHT: (C)1999,JPOAbstract translation: 要解决的问题：通过将误排列中的地址信息与可能改变的地址进行比较，消除加载队列并取消可能通过使用非法数据终止的指令。 解决方案：无论何时调度指令，都会在一个误排表中生成一个项目。 当在数据高速缓存206中命中指令时，在下一个周期将该指令项从错排列中移除。 当在数据高速缓存206中错过指令时，实际地址，有效地址和其他信息留在错排列表中。 处理器总是扫描错误列表中的项目的地址信息，并尝试以相应的周期访问存储在误排列中的有效地址的高速缓存。 可以在高速缓存206中获取关于错排列中的各个项目的数据，并将其传送到格式器210。
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公开(公告)号：CA2260308C
公开(公告)日：2001-10-09
申请号：CA2260308
申请日：1999-01-25
Applicant: IBM
Inventor： RAY DAVID SCOTT , TUNG SHIH-HSIUNG STEPHEN , WILLIAMSON BARRY DUANE
Abstract: One aspect of the invention relates to a method for processing load instructions in a superscalar processor having a data cache and a register file. In one embodiment, the method includes the steps of dispatching a misaligned load instruction to access a block of data that is misaligned in the cache; while continuing to dispatch aligned instructions: generating a first access and a final access to the cache in response to the misaligned load instruction; storing data retrieved from the first access until data from the final access is available; reassembling the data from the firs t and final access into the order required by the load instruction; and storing the re-assembled data to the register file.
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公开(公告)号：CA2260541C
公开(公告)日：2004-08-10
申请号：CA2260541
申请日：1999-02-01
Applicant: IBM
Inventor： CHIAROT KEVIN ARTHUR , WILLIAMSON BARRY DUANE , RAY DAVID SCOTT , TUNG SHIH-HSIUNG STEPHEN
Abstract: The present invention is directed towards a means to detect and reorder out of order instructions that may violate data coherency. The invention comprises a mis- queue table for holding entries of instruction data, each entry corresponding to an instruction in a computer microprocessor. The instruction data in each entry comprises: i) address information for the instruction; ii) ordering information for the instruction, indicating the order of the instruction relative to other instructions in the mis-queue table; iii) data modification information for the instruction, for indicating a possibility of modified data; and iv) out of order information, for indicating that a newer instruction has completed before the corresponding older instruction to the entry. The invention also comprises an out of order comparator for comparing an address of a completed instruction to any address information entries in the miss queue. If a completed instruction accesses the same address as another instruction, as indicated in the address information in the mis-queue table, and the completed instruction is newer than the matched instruction, the out of order field is marked indicating this condition exists. The invention comprises a modification comparator. This compares addresses from data altering events to thoseaddresses in the entries in the mis-queue table. On a match, the modification field of the corresponding entry is marked to indicate this condition exists. When an instruction entry indicates that the corresponding instruction's data is modified, and that the instruction is out of order, all subsequent instructions are cancelled.
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公开(公告)号：HK1019799A1
公开(公告)日：2000-02-25
申请号：HK99104881
申请日：1999-10-28
Applicant: IBM
Inventor： TUNG SHIH-HSIUNG STEPHEN , RAY DAVID SCOTT , CHIAROT KEVIN ARTHUR , WILLIAMSON BARRY DUANE
Abstract: The present invention is directed towards a means to detect and reorder out of order instructions that may violate data coherency. The invention comprises a mis-queue table for holding entries of instruction data, each entry corresponding to an instruction in a computer microprocessor. The instruction data in each entry comprises: i) address information for the instruction; ii) ordering information for the instruction, indicating the order of the instruction relative to other instructions in the mis-queue table; iii) data modification information for the instruction, for indicating a possibility of modified data; and iv) out of order information, for indicating that a newer instruction has completed before the corresponding older instruction to the entry. The invention also comprises an out of order comparator for comparing an address of a completed instruction to any address information entries in the miss queue. If a completed instruction accesses the same address as another instruction, as indicated in the address information in the mis-queue table, and the completed instruction is newer than the matched instruction, the out of order field is marked indicating this condition exists.The invention comprises a modification comparator. This compares addresses from data altering events to those addresses in the entries in the mis-queue table. On a match, the modification field of the corresponding entry is marked to indicate this condition exists. When an instruction entry indicates that the corresponding instruction's data is modified, and that the instruction is out of order, all subsequent instructions are cancelled.
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Patent Agency Ranking
公开(公告)号：AT209794T
公开(公告)日：2001-12-15
申请号：AT94306765
申请日：1994-09-15
Applicant: IBM
Inventor： RAY DAVID SCOTT , THATCHER LARRY EDWARD , WARREN HENRY STANLEY JR
IPC: G06F9/38
Abstract: A multiple execution unit processing system is provided wherein each execution unit 17, 19 has an associated instruction buffer 2, 4 and all instruction are executed in order. The first execution unit (unit 0) will always contain the oldest instruction and the second unit (unit 1) the newest. Processor instructions, such as load, store, add and the like are provided to each of the instruction buffers (0,1) from an instruction cache buffer. The first instruction (oldest) is placed in buffer 0 and the next (second) instruction is stored in buffer 1. It is determined during the decode stage whether the instructions are dependent on an immediately preceding instruction. If both instructions are independent of other instructions, then they can execute in parallel. However, if the second instruction is dependent on the first, then (subsequent to the first instruction being executed) it is laterally shifted to the first instruction buffer. Instructions are also defined as being dependent on an unavailable resource. In most cases these "unavailable" instructions are allowed to be executed in parallel on the execution units.
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公开(公告)号：SG70151A1
公开(公告)日：2000-01-25
申请号：SG1999000477
申请日：1999-02-05
Applicant: IBM
Inventor： TUNG SHIH-HSIUNG STEPHEN , RAY DAVID SCOTT , CHIAROT KEVIN ARTHUR , WILLIAMSON BARRY DUANE
Abstract: The present invention is directed towards a means to detect and reorder out of order instructions that may violate data coherency. The invention comprises a mis-queue table for holding entries of instruction data, each entry corresponding to an instruction in a computer microprocessor. The instruction data in each entry comprises: i) address information for the instruction; ii) ordering information for the instruction, indicating the order of the instruction relative to other instructions in the mis-queue table; iii) data modification information for the instruction, for indicating a possibility of modified data; and iv) out of order information, for indicating that a newer instruction has completed before the corresponding older instruction to the entry. The invention also comprises an out of order comparator for comparing an address of a completed instruction to any address information entries in the miss queue. If a completed instruction accesses the same address as another instruction, as indicated in the address information in the mis-queue table, and the completed instruction is newer than the matched instruction, the out of order field is marked indicating this condition exists.The invention comprises a modification comparator. This compares addresses from data altering events to those addresses in the entries in the mis-queue table. On a match, the modification field of the corresponding entry is marked to indicate this condition exists. When an instruction entry indicates that the corresponding instruction's data is modified, and that the instruction is out of order, all subsequent instructions are cancelled.
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公开(公告)号：ID21939A
公开(公告)日：1999-08-12
申请号：ID981693
申请日：1998-12-28
Applicant: IBM
Inventor： TUNG SHIH HSIUNG STEPHEN , RAY DAVID SCOTT , CHIAROT KEVIN ARTHUR , WILLIAMSON BARRY DUANE
Abstract: The present invention is directed towards a means to detect and reorder out of order instructions that may violate data coherency. The invention comprises a mis-queue table for holding entries of instruction data, each entry corresponding to an instruction in a computer microprocessor. The instruction data in each entry comprises: i) address information for the instruction; ii) ordering information for the instruction, indicating the order of the instruction relative to other instructions in the mis-queue table; iii) data modification information for the instruction, for indicating a possibility of modified data; and iv) out of order information, for indicating that a newer instruction has completed before the corresponding older instruction to the entry. The invention also comprises an out of order comparator for comparing an address of a completed instruction to any address information entries in the miss queue. If a completed instruction accesses the same address as another instruction, as indicated in the address information in the mis-queue table, and the completed instruction is newer than the matched instruction, the out of order field is marked indicating this condition exists.The invention comprises a modification comparator. This compares addresses from data altering events to those addresses in the entries in the mis-queue table. On a match, the modification field of the corresponding entry is marked to indicate this condition exists. When an instruction entry indicates that the corresponding instruction's data is modified, and that the instruction is out of order, all subsequent instructions are cancelled.
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公开(公告)号：CA2260541A1
公开(公告)日：1999-08-10
申请号：CA2260541
申请日：1999-02-01
Applicant: IBM
Inventor： TUNG SHIH-HSIUNG STEPHEN , RAY DAVID SCOTT , WILLIAMSON BARRY DUANE , CHIAROT KEVIN ARTHUR
Abstract: The present invention is directed towards a means to detect and reorder out of order instructions that may violate data coherency. The invention comprises a misqueue table for holding entries of instruction data, each entry corresponding to an instruction in a computer microprocessor. The instruction data in each entry comprises: i) address information for the instruction; ii) ordering information for the instruction, indicating the order of the instruction relative to other instructions in the mis-queue table; iii) data modification information for the instruction, for indicating a possibility of modified data; and iv) out of order information, for indicating that a newer instruction has completed before the corresponding older instruction to the entry. The invention also comprises an out of order comparator for comparing an address of a completed instruction to any address information entries in the miss queue. If a completed instruction accesses the same address as another instruction, as indicated in the address information in the mis-queue table, and the completed instruction is newer than the matched instruction, the out of order field is marked indicating this condition exists. The invention comprises a modification comparator. This compares addresses from data altering events to those addresses in the entries in the mis-queue table. On a match, the modification field of the corresponding entry is marked to indicate this condition exists. When an instruction entry indicates that the corresponding instruction's data is modified, and that the instruction is out of order, all subsequent instructions are cancelled.
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公开(公告)号：BR9403515A
公开(公告)日：1995-06-20
申请号：BR9403515
申请日：1994-09-12
Applicant: IBM
Inventor： RAY DAVID SCOTT , SPENCER ALEXANDER KOOS
Abstract: An apparatus and method provides additional logic in both execution units 9,11 of a dual execution unit processor in order to determine if the instruction is interruptable. Additionally, backout logic 17,19 is provided for saving the contents of unique registers 13,15. The backout logic 17,19 uses two decodes to determine if the instruction currently executing modifies the unique registers 13,15. It is possible for a single instruction to modify more than one unique register 13,15. The backout logic of the present invention resides in both of the execution units 9,11 and particularly in the unit which contains the unique register being modified by the executing instruction. If an instruction is being executed which modifies one of the unique registers 13,15, then the contents of that register are saved in a backout latch 17,19. A cancel signal is then provided if the interruptable instruction executes without causing an interrupt. However, if the interruptable instruction does cause an interrupt, then the contents of the backout latch are reloaded into the execution units.
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