公开(公告)号：US3736573A

公开(公告)日：1973-05-29

申请号：US3736573D

申请日：1971-11-11

Applicant: IBM

Inventor： BLOUNT F ,  GELLER H ,  MOORE R ,  LEUNG H ,  LEWIS S ,  REDMOND J

IPC: G11C11/41 ,  G11C11/411 ,  G11C11/414 ,  G11C11/415 ,  G11C11/416 ,  H03K3/288 ,  H03K17/62 ,  G11C11/40

CPC classification number: G11C11/4116 ,  G11C11/415 ,  G11C11/416 ,  H03K3/288 ,  H03K17/6221

Abstract: A data storage circuit utilizing a bistable memory cell and a resistor sensing bit switch preamplifier for performing read and write operations. The cell contains two double-emitter semiconductor elements having their bases and collectors crosscoupled to form a bistable circuit. Each element has one emitter connected in common to a resistor terminated word line to permit bilevel conduction of the elements from a low level standby state to a higher level power-up state for access operations. The second emitter of each element is coupled through collectoremitter paths of a pair of amplifying and switching transistors to corresponding ones of resistor terminated bit sense lines. The amplifying transistors are concurrently biased on and off by a gating transistor under selective control of a bit driver decoding circuit. In read operations, the stored data is sensed at the bit sense line resistors by a final sense amplifier. For write operations, a write driver is provided to provide appropriate voltages at the bit sense line resistor as required for storage of required data in the memory cell. The final sense amplifier is adapted to be isolated from the circuit by connection to the bit lines through the collector-emitter path of a normally forward-biased control transistor which is reversebiased during write operations.

Abstract translation: 利用双稳态存储单元的数据存储电路和用于执行读和写操作的电阻感测位开关前置放大器。 该电池包含两个双发射极半导体元件，其具有交叉耦合的基极和集电极以形成双稳态电路。 每个元件具有一个共同连接到电阻器端接字线的发射极，以允许元件从低电平待机状态的双电平传导到用于存取操作的较高电平上电状态。 每个元件的第二发射极通过一对放大和开关晶体管的集电极 - 发射极路径耦合到对应的电阻端接的位感测线。 在位驱动器解码电路的选择性控制下，放大晶体管同时被门控晶体管偏置。 在读取操作中，存储的数据通过最终读出放大器在位感测线电阻器处被感测。