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    VIRTUAL MEMORY DATA PROCESSING SYSTEM
    1.
    发明专利
    VIRTUAL MEMORY DATA PROCESSING SYSTEM 未知

    公开(公告)号：DE2965382D1

    公开(公告)日：1983-06-16

    申请号：DE2965382

    申请日：1979-09-24

    Applicant: IBM

    Inventor： LEWIS DAVID OTTO ,  REED JOHN WALTER

    IPC: G06F13/12 ,  G06F12/10 ,  G06F13/10 ,  G06F3/04

    Abstract: This invention relates to a virtual memory data processing system, and the specification describes such a system in which apparatus is provided for enabling I/O adapters (4) to use virtual addresses. After each I/0 data transfer, the main memory (5) address involved in the transfer is incremented. This address is maintained in I/O register associated with the I/O adapter (4) performing the transfer. If a page boundary is crossed in the process of incrementing, the channel (3) forms an I/O event indicating the page crossing and calling for translation of the incremented address. When the I/O adapter (4) involved in the page crossing attempts a further data transfer, the channel (3) disconnects the I/O adapter. The channel (3) holds the I/O adapter (4) disconnected until the page crosing denoted by the I/O event has been resolved by translating the incremented address and providing a new main memory address for continuing the data transfer. Because the disconnect is effected by ignoring the priority of the disconnected adapter when it requests service, other adapters of lower priority can be serviced by the channel during the disconnect. When completion of the address translation is signalled, the I/O adapter is no longer held disconnected.

    INPUT/OUTPUT-SYSTEM FOR A DATA PROCESSING SYSTEM
    2.
    发明专利
    INPUT/OUTPUT-SYSTEM FOR A DATA PROCESSING SYSTEM 未知

    公开(公告)号：DE2965381D1

    公开(公告)日：1983-06-16

    申请号：DE2965381

    申请日：1979-09-24

    Applicant: IBM

    Inventor： LEWIS DAVID OTTO ,  REED JOHN WALTER ,  WALLIN GARY WILLIAM

    IPC: G06F13/00 ,  G06F13/12 ,  G06F3/04

    Abstract: This invention relates to a data processing system. … In such a system having an addressable storage (5) for storing instructions, data and input-output (I/O) commands, a central processing unit (CPU) (1) which fetches an executes instructions, and channel means (3) connecting I/O adapters (4) to the storage and the CPU, an apparatus is provided which transfers I/O commands to the I/O adapters (4) whereby the I/O command is either accepted immediately or is queued by the I/O adapter. A queued command is taken up by the I/O adapter (4) when no other data transfer operation is pending. To take up a queue command, the I/O adapter (4) initiates a fetch of the pending command by invoke a standard data-transfer-from-storage sequences. The channel means (3) responds to the fetch initiated by the I/O adapter (4) to send the pending command to the I/O adapter.

    COMMAND QUEUEING FOR I/O ADAPTERS
    5.
    发明专利
    COMMAND QUEUEING FOR I/O ADAPTERS 未知

    公开(公告)号：AU5055979A

    公开(公告)日：1980-05-01

    申请号：AU5055979

    申请日：1979-09-04

    Applicant: IBM

    Inventor： LEWIS DAVID OTTO ,  REED JOHN WALTER ,  WALLIN GARY WILLIAM

    IPC: G06F13/00 ,  G06F13/12 ,  G06F3/00 ,  G06F9/18

    Abstract: This invention relates to a data processing system. … In such a system having an addressable storage (5) for storing instructions, data and input-output (I/O) commands, a central processing unit (CPU) (1) which fetches an executes instructions, and channel means (3) connecting I/O adapters (4) to the storage and the CPU, an apparatus is provided which transfers I/O commands to the I/O adapters (4) whereby the I/O command is either accepted immediately or is queued by the I/O adapter. A queued command is taken up by the I/O adapter (4) when no other data transfer operation is pending. To take up a queue command, the I/O adapter (4) initiates a fetch of the pending command by invoke a standard data-transfer-from-storage sequences. The channel means (3) responds to the fetch initiated by the I/O adapter (4) to send the pending command to the I/O adapter.

    COMMAND QUEUEING FOR I/O ADAPTERS
    7.
    发明专利
    COMMAND QUEUEING FOR I/O ADAPTERS 未知

    公开(公告)号：AU527907B2

    公开(公告)日：1983-03-31

    申请号：AU5055979

    申请日：1979-09-04

    Applicant: IBM

    Inventor： LEWIS DAVID OTTO ,  REED JOHN WALTER ,  WALLIN GARY WILLIAM

    IPC: G06F13/00 ,  G06F13/12 ,  G06F3/00 ,  G06F9/18

    Abstract: This invention relates to a data processing system. … In such a system having an addressable storage (5) for storing instructions, data and input-output (I/O) commands, a central processing unit (CPU) (1) which fetches an executes instructions, and channel means (3) connecting I/O adapters (4) to the storage and the CPU, an apparatus is provided which transfers I/O commands to the I/O adapters (4) whereby the I/O command is either accepted immediately or is queued by the I/O adapter. A queued command is taken up by the I/O adapter (4) when no other data transfer operation is pending. To take up a queue command, the I/O adapter (4) initiates a fetch of the pending command by invoke a standard data-transfer-from-storage sequences. The channel means (3) responds to the fetch initiated by the I/O adapter (4) to send the pending command to the I/O adapter.

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