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公开(公告)号：DE3381229D1
公开(公告)日：1990-03-29
申请号：DE3381229
申请日：1983-12-21
Applicant: IBM
Inventor： GODLSBEY MICHAEL ALFRED , JONES EUGENE REESE , MICKA WILLIAM FRANK , ROBINSON THOMAS SCOTT
IPC: G06K9/34
Abstract: A method of locating a single image in a field of images by scanning the field in a stream of video elements, interrogating said elements with a logic to produce a set of cells each representing a relatively small portion of a single image, and recombining said cells with another logic to produce a block representing an area containing said single image separated from its neighbours. An apparatus for locating a single image in a field of images, comprising a scanner (110) to produce a stream of video elements representing said field, an image memory (130) to store said video elements, a logic (151, 160) responsive to said elements to produce a set of cells each representing a relatively small portion of a single image, and another logic (153) responsive to said set of cells to produce a block representing an area containing said single image separated from its neighbours.
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公开(公告)号：CH620542A5
公开(公告)日：1980-11-28
申请号：CH757177
申请日：1977-06-21
Applicant: IBM
Inventor： MICKA WILLIAM FRANK , ROBINSON THOMAS SCOTT
Abstract: 1533833 Storage arrangements INTERNATIONAL BUSINESS MACHINES CORP 15 June 1977 [30 June 1976] 25032/77 Heading G4A In apparatus for rotating by 90 degrees video data having 2048 bits per scan line, the data is deserialized and stored, parallel by byte, in successive row locations of a memory (40, Fig. 2, not shown) holding 2048 bytes in 8 rows, by incrementing address counter (41). Read out into registers (50-57) is effected column by column by incrementing the top 3 bits of the address counter for each state of the bottom 8 bits from which the rotated data may be read to an 8 by 8 storage array (60-67) so that corresponding bits of the 8 read out bytes are stored in the same column. Preferably two memories 118, 122 (Fig. 3) are used, one being read out whilst the other is loaded under the control of two counters (204, 206, Fig. 4, not shown) the first incremented normally for loading and the second having its top 3 bits incremented for each state of the bottom 8 bits for unloading, the top 3 bits being decoded to select to which if registers 150-157 the read out data is fed.
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公开(公告)号：AU5188079A
公开(公告)日：1980-05-15
申请号：AU5188079
申请日：1979-10-17
Applicant: IBM
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Patent Agency Ranking
公开(公告)号：DE2964218D1
公开(公告)日：1983-01-13
申请号：DE2964218
申请日：1979-09-24
Applicant: IBM
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公开(公告)号：DE2963075D1
公开(公告)日：1982-07-29
申请号：DE2963075
申请日：1979-09-24
Applicant: IBM
Inventor： DIEZ MARK FERNANDO , LEWIS DAVID OTTO , ROBINSON THOMAS SCOTT
Abstract: In order to monitor non-uniform I/O device activity with low time overheads, data processing appparatus is provided iriicluding a hardware monitor including a memory array (4) having a location for each I/O device loaded with control data from the central processor at start I/O time. The monitor is driven by a free running ring (80) and maintains in the location for each I/O device an updated count of running time in terms of the output of an interval timer (76) until command end or other ordered clear. The monitor searches the array location cyclically, comparing the processor supplied data and the currently generated data, signalling the processor only when the two values are equal (or current exceed specified). Automatic house-keeping is provided for.
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公开(公告)号：DE3071860D1
公开(公告)日：1987-01-22
申请号：DE3071860
申请日：1980-12-12
Applicant: IBM
Inventor： LEWIS DAVID OTTO , PERTZBORN JAMES JOHN , ROBINSON THOMAS SCOTT , HEISE NYLES NORBERT , HOFFMAN ROY LOUIS , KISS ISTVAN STEVE
Abstract: In virtual storage data processing apparatus including real main storage, 10 a virtual address translation unit VAT 15 and a common I/O control unit 110 serving plural I/O devices, 150 the virtual address translation unit includes a resolved address register for each I/O device, a pool of resolved address registers and control logic responsive to a device specific CPU I/O command for initiating chaines I/O data transfers to cause the VAT apparatus to translate a first virtual address to be used in the chained data transfer operation and load the translated (resolved) address the appropriate resolved address register and responsive to a command from the shared control unit indicating that one of the commanded I/O devices is ready for data transfer to become nonresponsive to further CPU I/O commands and cause the VAT to resolve a succession of virtual addresses for the data transfer and to load the resolved addresses into resolved address registers of the pool whereby a data transfer operation can commence using the resolved address in the register unique to the I/O device which is first ready for data transfer and thereafter continue with data transfers using resolved addresses from the registers shared by all of the I/O devices but captured for use by the I/O device first ready for data transfer. Upon the data transfers being completed for that I/O device, the VAT resolves a succession of virtual addresses and loads them into the shared registers for use during data transfers by the next ready I/O device in response to a command from the shared I/O control unit.
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公开(公告)号：AU534577B2
公开(公告)日：1984-02-09
申请号：AU5188079
申请日：1979-10-17
Applicant: IBM
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公开(公告)号：DE2725395A1
公开(公告)日：1978-01-05
申请号：DE2725395
申请日：1977-06-04
Applicant: IBM
Inventor： MICKA WILLIAM FRANK , ROBINSON THOMAS SCOTT
Abstract: 1533833 Storage arrangements INTERNATIONAL BUSINESS MACHINES CORP 15 June 1977 [30 June 1976] 25032/77 Heading G4A In apparatus for rotating by 90 degrees video data having 2048 bits per scan line, the data is deserialized and stored, parallel by byte, in successive row locations of a memory (40, Fig. 2, not shown) holding 2048 bytes in 8 rows, by incrementing address counter (41). Read out into registers (50-57) is effected column by column by incrementing the top 3 bits of the address counter for each state of the bottom 8 bits from which the rotated data may be read to an 8 by 8 storage array (60-67) so that corresponding bits of the 8 read out bytes are stored in the same column. Preferably two memories 118, 122 (Fig. 3) are used, one being read out whilst the other is loaded under the control of two counters (204, 206, Fig. 4, not shown) the first incremented normally for loading and the second having its top 3 bits incremented for each state of the bottom 8 bits for unloading, the top 3 bits being decoded to select to which if registers 150-157 the read out data is fed.
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