公开(公告)号：JPS62160819A

公开(公告)日：1987-07-16

申请号：JP27426286

申请日：1986-11-19

Applicant: IBM

Inventor： BERANGER HERVE L ,  GAUDENZI GENE J ,  REEDY DENNIS C ,  SCHETTLER HELMUT

IPC: H03K19/0175 ,  H03K17/16 ,  H03K19/003 ,  H03K19/018 ,  H03K19/0185 ,  H03K19/088

公开(公告)号：CA1089032A

公开(公告)日：1980-11-04

申请号：CA285806

申请日：1977-08-30

Applicant: IBM

Inventor： REEDY DENNIS C

IPC: H03K19/088 ,  H03K19/08 ,  H03K19/12 ,  H03K19/36

Abstract: TRANSISTOR-TRANSISTOR-LOGIC CIRCUIT Disclosed is a transistor-transistor-logic (TTL) circuit which is testable by D.C. Testing Techniques. The improvement includes a high impedance network for providing sufficient base drive to drive the output transistor into conduction when the malfunctioning input transistor fails to provide a turn-off logic level. The high impedance network can be a Schottky barrier diode and an epitaxial resistor connected in a series path between a potential supply and the base region of the output transistor.

公开(公告)号：CA1250351A

公开(公告)日：1989-02-21

申请号：CA457030

申请日：1984-06-20

Applicant: IBM

Inventor： GAUDENZI GENE J ,  NORSWORTHY JOHN P ,  PHAN NGHIA V ,  REEDY DENNIS C

IPC: H03K5/02 ,  H03K17/04 ,  H03K17/60 ,  H03K17/615 ,  H03K19/088 ,  H03K19/092

Abstract: LOW POWER OFF-CHIP DRIVER CIRCUIT Power dissipation in an off-chip driver circuit is decreased by utilizing a selectively switched transistor to discharge the base of the output pull-down transistor, and by using a large resistance in the base current path for the first stage of the Darlington pull-up transistors. An additional transistor having a larger emitter area and coupled to a lower potential source is connected in parallel with the normal phase-splitter transistor to provide additional output current sinking capability, and a current mirror is connected to control the current through both the phase splitting transistor and the additional transistor to control the turn-on transition of the pull-down output transistor.

公开(公告)号：FR2363942A1

公开(公告)日：1978-03-31

申请号：FR7722459

申请日：1977-07-13

Applicant: IBM

Inventor： REEDY DENNIS C

IPC: H03K19/088 ,  H03K19/08

Abstract: Disclosed is a transistor-transistor-logic (TTL) circuit which is testable by D. C. Testing Techniques. The improvement includes a high impedance network for providing sufficient base drive to drive the output transistor into conduction when the malfunctioning input transistor fails to provide a turn-off logic level. The high impedance network can be a Schottky barrier diode and an epitaxial resistor connected in a series path between a potential supply and the base region of the output transistor.

公开(公告)号：DE3672048D1

公开(公告)日：1990-07-19

申请号：DE3672048

申请日：1986-09-16

Applicant: IBM

Inventor： GAUDENZI GENE J ,  REEDY DENNIS C

IPC: H03K17/04 ,  H03K19/013 ,  H03K19/082

Abstract: A logic inverter or NOR circuit exhibits push-pull output characteristics by employing a saturated (T3) feedback technique. This approach allows for emitter follower like up level drive (by T2) and transient low impedance down level drive (through T1 and T3). The disclosed saturated feedback technique improves capacitive drive capability, reduces both load and circuit delay and reduces circuit power dissipation.

公开(公告)号：CA1252522A

公开(公告)日：1989-04-11

申请号：CA507287

申请日：1986-04-22

Applicant: IBM

Inventor： GAUDENZI GENE J ,  REEDY DENNIS C

IPC: H03K17/04 ,  H03K19/013 ,  H03K19/082

Abstract: The logic circuit disclosed exhibits push-pull output characteristic by employing a saturated feedback technique. This approach allows for emitter follower like up level drive and transient low impedance down level drive. The disclosed saturated feedback technique improves capacitive drive capability, reduces both load and circuit delay and reduces circuit power dissipation.