公开(公告)号：US3899777A

公开(公告)日：1975-08-12

申请号：US44603374

申请日：1974-02-25

Applicant: IBM

Inventor： FEICHT ERWIN ,  HAUG WERNER OTTO ,  REMSHARDT ROLF ,  SCHETTLER HELMUT

IPC: G11C11/41 ,  G11C11/414 ,  G11C11/419 ,  H03F3/45 ,  G11C7/06

CPC classification number: G11C11/419 ,  H03F3/45479

Abstract: In a monolithic semiconductor storage the bit lines are selectively connected in pairs to the inputs of a read amplifier. In their separated state the potentials of the read lines (VB) and of the associated input lines of the read amplifier (VBS1, VBS2) show the same value and are derived from a common potential (VH). Potentials VB as well as VBS1 and VBS2 are derived via the same respective number of diode voltage drops from potential VH.

Abstract translation: 在单片半导体存储器中，位线被选择性地与读取放大器的输入成对连接。 在分离状态下，读取放大器（VBS1，VBS2）的读取线（VB）和相关输入线的电位显示相同的值，并从公共电位（VH）导出。 电位VB以及VBS1和VBS2是通过从电位VH相同的相应数量的二极管电压降导出的。

公开(公告)号：WO0213041A2

公开(公告)日：2002-02-14

申请号：PCT/EP0108780

申请日：2001-07-28

Applicant: IBM ,  IBM DEUTSCHLAND

Inventor： KROELL KARL-EUGEN ,  PILLE JUERGEN ,  SCHETTLER HELMUT

IPC: G06F17/50 ,  G06F19/00 ,  H01L29/00 ,  G06F17/00

CPC classification number: G06F17/5022 ,  G06F17/5036

Abstract: An improved hardware circuit simulation method in particular for history-dependent and cyclic operation sensible hardware circuits, like SOI-type hardware, for example, checks for correct cyclic boundary conditions by performing (110) a first run of a prior art DC simulation with input voltage conditions belonging to CYCLE START, and by carrying out (120) a second DC simulation with input voltage conditions belonging to CYCLE STOP. After comparing (130) the results, e.g., comparing the node voltages, any mismatches can be determined which serve as a hint to non-compatibility with cyclic operation. Thus, the design is able to be re-designed (140) before being simulated in vain with a great amount of work and computing time. A transient simulation (150) can be appended for automated correction (160, 170) of dynamic errors.

Abstract translation: 改进的硬件电路仿真方法，特别是用于历史依赖和循环操作的显性硬件电路（例如，SOI型硬件），例如通过执行（110）先前技术的DC仿真的第一次运行来检查正确的循环边界条件 属于循环启动的电压条件，并通过执行属于循环停止的输入电压条件进行（120）第二次直流模拟。 在比较（130）结果（例如，比较节点电压）之后，可以确定哪些不匹配作为与循环操作不兼容的暗示。 因此，在大量的工作和计算时间被模拟之前，设计能够被重新设计（140）。 可以附加瞬态模拟（150）以进行动态错误的自动校正（160,170）。

公开(公告)号：JPS62160819A

公开(公告)日：1987-07-16

申请号：JP27426286

申请日：1986-11-19

Applicant: IBM

Inventor： BERANGER HERVE L ,  GAUDENZI GENE J ,  REEDY DENNIS C ,  SCHETTLER HELMUT

IPC: H03K19/0175 ,  H03K17/16 ,  H03K19/003 ,  H03K19/018 ,  H03K19/0185 ,  H03K19/088

公开(公告)号：DE3173631D1

公开(公告)日：1986-03-13

申请号：DE3173631

申请日：1981-09-10

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： BLUM ARNOLD ,  SCHETTLER HELMUT

IPC: H03K19/00 ,  G01R31/316 ,  G01R31/317 ,  G01R31/319 ,  H03K19/0175 ,  G01R31/28

Abstract: An integrated circuit chip includes a tristate driver which assumes an active logical state in response to a data signal at its data input and assumes a high impedance state in response to a control signal at its control input. The integrated circuit chip also includes a control signal generating network which is connected to the tristate driver's control input for producing the control signal. The control signal generating network may be tested by connecting the control signal generating network to the data input and overriding the control input to prevent the tristate driver from assuming the high impedance state. Thus, for testing purposes, the proper response of the control signal generating circuit may be ascertained by monitoring the active state of the tristate driver.

公开(公告)号：DE3168838D1

公开(公告)日：1985-03-28

申请号：DE3168838

申请日：1981-01-30

Applicant: IBM DEUTSCHLAND ,  IBM

Inventor： MIERSCH EKKEHARD DR ,  POLLMANN KURT ,  SCHETTLER HELMUT ,  ZUHLKE RAINER DR

IPC: H03F3/217 ,  H03F3/20 ,  H03F3/30 ,  H03K5/02 ,  H03K17/16 ,  H03K19/0175 ,  H03K19/088 ,  H03K6/02 ,  H03K19/003

Abstract: Push-pull driver with reduced noise generation resulting from driver switching. A further transistor is arranged between the driver output transistor (which becomes conductive at the low output level) and the chip ground line. Its base is connected to a reference voltage source the other pole of which is connected to the ground plane of the circuit card to which the corresponding semiconductor chip is attached. If a noise voltage is generated on the chip ground line, the emitter potential of the further transistor is pulled up. As its base potential is maintained at a fixed value by the applied reference potential, this transistor becomes less conductive. As a result, the rate of current change in the output stage is reduced. The slowed down current rise, leads to a reduced noise voltage developing on the common chip ground line. According to another embodiment of the invention the output transistor and said further transistor are combined to form one transistor whose base is maintained at a fixed voltage by means of two series-connected Schottky diodes.

公开(公告)号：AU7755801A

公开(公告)日：2002-02-18

申请号：AU7755801

申请日：2001-07-28

Applicant: IBM

Inventor： PILLE JURGEN ,  SCHETTLER HELMUT

IPC: G06F17/50 ,  G06F19/00 ,  H01L29/00 ,  G06F17/00

公开(公告)号：DE3780482T2

公开(公告)日：1993-03-11

申请号：DE3780482

申请日：1987-01-13

Applicant: IBM

Inventor： DANSKY ALLAN H ,  SAVALLE MARTINE MARIE FRANCOIS ,  SCHETTLER HELMUT

IPC: H03K3/2885 ,  H03K19/013 ,  H03K19/082 ,  H03K19/00 ,  H03K3/288

Abstract: A "dotted or" logic circuit comprising Current Controlled Gate (CCG) circuits (A,B) is described. In accordance with the present invention, Schottky diodes (D1A,D1B) are cross-coupled between the dotted CCG circuits.Specifically, a Schottky diode (D1A,D1B) of one CCG circuit to the emitter (A2,B2) of the input transistors (T1,T2) of another CCG circuit and vice versa.

公开(公告)号：DE59309544D1

公开(公告)日：1999-06-02

申请号：DE59309544

申请日：1993-05-21

Applicant: IBM

Inventor： KOETZLE GUNTHER ,  KREUTER VOLKER ,  LUDWIG THOMAS ,  SCHETTLER HELMUT

IPC: G05F3/20 ,  H01L27/02

Abstract: PCT No. PCT/DE93/00443 Sec. 371 Date Jul. 17, 1995 Sec. 102(e) Date Jul. 17, 1995 PCT Filed May 21, 1993 PCT Pub. No. WO94/01890 PCT Pub. Date Jan. 20, 1994An integrated semiconductor circuit for reducing power consumption, employing CMOS technology in which a transistor pair can be operated stably at different supply voltages. At each supply voltage the transistors have an associated threshold voltage which can be set via the well and substrate bias voltages. The substrate of the transistor pair is connected to a substrate bias voltage generator circuit and the well is connected to a well bias voltage generator circuit. An input signal representing the level of the supply voltage sets the respective bias voltages corresponding to the level of the supply voltage. Thus, the threshold voltage of each transistor is adapted to the existing supply voltage, thereby ensuring stable operation of the transistor pair. A battery driven data processing system with the integrated semiconductor circuit can attain an approximate 100 fold extension of the operating time of the battery.

公开(公告)号：DE4221575C2

公开(公告)日：1995-02-09

申请号：DE4221575

申请日：1992-07-01

Applicant: IBM

Inventor： KOETZLE GUENTHER ,  KREUTER VOLKER ,  LUDWIG THOMAS ,  SCHETTLER HELMUT

IPC: G05F3/20 ,  H01L27/02 ,  H01L23/58 ,  H01L27/092 ,  G11C5/14 ,  G06F1/32

Abstract: PCT No. PCT/DE93/00443 Sec. 371 Date Jul. 17, 1995 Sec. 102(e) Date Jul. 17, 1995 PCT Filed May 21, 1993 PCT Pub. No. WO94/01890 PCT Pub. Date Jan. 20, 1994An integrated semiconductor circuit for reducing power consumption, employing CMOS technology in which a transistor pair can be operated stably at different supply voltages. At each supply voltage the transistors have an associated threshold voltage which can be set via the well and substrate bias voltages. The substrate of the transistor pair is connected to a substrate bias voltage generator circuit and the well is connected to a well bias voltage generator circuit. An input signal representing the level of the supply voltage sets the respective bias voltages corresponding to the level of the supply voltage. Thus, the threshold voltage of each transistor is adapted to the existing supply voltage, thereby ensuring stable operation of the transistor pair. A battery driven data processing system with the integrated semiconductor circuit can attain an approximate 100 fold extension of the operating time of the battery.

公开(公告)号：BR8706324A

公开(公告)日：1988-07-19

申请号：BR8706324

申请日：1987-11-24

Applicant: IBM

Inventor： KLEIN KLAUS ,  POLLMANN KURT ,  SCHETTLER HELMUT ,  SCHULZ UWE ,  WAGNER OTTO M ,  ZUEHLKE RAINER

IPC: H01L21/82 ,  G06F17/50 ,  H01L21/822 ,  H01L27/04 ,  H01L21/92

Abstract: For the physical design of a VLSI chip a method is provided to implement a high density master image that contains logic and RAMs. In a hierarchical top-down design methodology the circuitry to be contained on the chip is logically devided into partitions that are manageable by the present automatic design systems and programs. Global wiring connection lines are from the beginning included into the design of the different individual partitions and treated there in the same way as circuits in that area. Thus the different partitions are designed in parallel. A floorplan is established that gives the different partitions a shape in such a way that they fit together without leaving any space between the different individual partitions. The chip need no extra space for global wiring and the partitions are immediataly attached to each other. The master image described is very flexible with respect to logic, RAM, ROM and other macros, and it offers some of the advantages of semicustom gate arrays and custom macro design. The thus designed chip shows no global wiring avenues between the partitions and has partitions of different porosity.