公开(公告)号：AU7747881A

公开(公告)日：1982-07-08

申请号：AU7747881

申请日：1981-11-13

Applicant: IBM

Inventor： BUSHAW KENNETH ALLEN ,  BRANSON WILLIAM IRVIN ,  REHAGE TED ANTHONY ,  SHOOK FRANKIE SHERWOOD

IPC: H04N1/00 ,  G06F13/12 ,  H04L29/00 ,  H04N1/32 ,  H04N1/40 ,  G06F3/00

Abstract: An electronic document distribution terminal includes a first adapter (12) coupled to data entry and document preparation means and a second adapter (15) coupled to data transmission means for communication, for example, with a similar terminal. Each of the adapters includes a processor for processing the data received from or for application to a coupled device. A peripheral processing memory (16) is employed to store data to be transferred between the adapters. This memory is under the control of a peripheral processing controller (10) which allocates memory blocks to the adapters under the control of CPU 20. Thus each adapter operates as a stand-alone unit sharing a common memory with the CPU and peripheral processing controller performing only system control functions.

公开(公告)号：DE3277991D1

公开(公告)日：1988-02-18

申请号：DE3277991

申请日：1982-02-05

Applicant: IBM

Inventor： BAUER WAYNE JOHN ,  DODT WILLIAM CARL ,  KIRKPATRICK CHARLES RONALD ,  REHAGE TED ANTHONY ,  ROBINSON FRANCIS LEROY ,  TAYLOR WILLIAM KING

IPC: G06F3/06 ,  G06F11/20 ,  G06F13/12 ,  G06F13/38 ,  G06F13/42

公开(公告)号：DE3176841D1

公开(公告)日：1988-09-15

申请号：DE3176841

申请日：1981-10-27

Applicant: IBM

Inventor： BUSHAW KENNETH ALLEN ,  BRANSON WILLIAM IRVIN ,  REHAGE TED ANTHONY ,  SHOOK FRANKIE SHERWOOD

IPC: H04N1/00 ,  G06F13/12 ,  H04L29/00 ,  H04N1/32 ,  H04N1/40 ,  G06F15/16

Abstract: An electronic document distribution terminal includes a first adapter (12) coupled to data entry and document preparation means and a second adapter (15) coupled to data transmission means for communication, for example, with a similar terminal. Each of the adapters includes a processor for processing the data received from or for application to a coupled device. A peripheral processing memory (16) is employed to store data to be transferred between the adapters. This memory is under the control of a peripheral processing controller (10) which allocates memory blocks to the adapters under the control of CPU 20. Thus each adapter operates as a stand-alone unit sharing a common memory with the CPU and peripheral processing controller performing only system control functions.

公开(公告)号：AU3219478A

公开(公告)日：1979-07-12

申请号：AU3219478

申请日：1978-01-05

Applicant: IBM

Inventor： CURLANDER PAUL JOSEPH ,  REHAGE TED ANTHONY

IPC: G06F11/30 ,  G06F11/07 ,  G06F11/32 ,  G06F13/00 ,  G06F11/06 ,  G07C3/00 ,  G07C11/00

Abstract: In a plural unit system, particularly of the data processing type, controlled units such as tape drives, constitute status reporting units (SRUs) which report status including error conditions to one or more status analyzing units such as computers (CPUs), programmable controllers, and the like. Each of the SRUs has a register, such as a shift register, associated therewith for receiving error status indications. The signal state of the shift register when all zeros indicates error-free status, any nonzero state signifies an error. An OR circuit receives signals from all of the bit positions of each of the respective shift registers and combines same into an SRU group error indicating signal. A second register, also a shift register, associated with the respective SRUs receives the output of the OR circuit in one of its bit positions, the bit position indicating the address of the reporting SRU. The output of the two shift registers associated with each of the SRUs are serialized onto one wire and supplied to an intermediate shift register. Combined signal status in the intermediate shift register are then supplied to one or more status analyzing units in a two byte format, i.e., one byte for the address and a second byte for the error status. An appropriate status analyzing unit then determines the error condition of the SRU. If more than one SRU is in error, then the address byte will have more than one binary one indicating state requiring further analysis by the respective status analyzing units.

公开(公告)号：AU539142B2

公开(公告)日：1984-09-13

申请号：AU7747881

申请日：1981-11-13

Applicant: IBM

Inventor： BUSHAW KENNETH ALLEN ,  BRANSON WILLIAM IRVIN ,  REHAGE TED ANTHONY ,  SHOOK FRANKIE SHERWOOD

IPC: H04N1/00 ,  G06F13/12 ,  H04L29/00 ,  H04N1/32 ,  H04N1/40 ,  G06F3/00

Abstract: An electronic document distribution terminal includes a first adapter (12) coupled to data entry and document preparation means and a second adapter (15) coupled to data transmission means for communication, for example, with a similar terminal. Each of the adapters includes a processor for processing the data received from or for application to a coupled device. A peripheral processing memory (16) is employed to store data to be transferred between the adapters. This memory is under the control of a peripheral processing controller (10) which allocates memory blocks to the adapters under the control of CPU 20. Thus each adapter operates as a stand-alone unit sharing a common memory with the CPU and peripheral processing controller performing only system control functions.

公开(公告)号：DE3064204D1

公开(公告)日：1983-08-25

申请号：DE3064204

申请日：1980-04-10

Applicant: IBM

Inventor： BIGELOW GEORGE ANDREW ,  REHAGE TED ANTHONY ,  SHOOK FRANKIE SHERWOOD

IPC: G06F3/06 ,  G06F5/06 ,  G06F5/16 ,  G06F13/00 ,  G06F13/38 ,  G11C9/00

公开(公告)号：DE2813418A1

公开(公告)日：1978-10-12

申请号：DE2813418

申请日：1978-03-29

Applicant: IBM

Inventor： CURLANDER PAUL JOSEPH ,  REHAGE TED ANTHONY

IPC: G06F11/30 ,  G06F11/07 ,  G06F11/32 ,  G06F13/00 ,  G06F11/00

Abstract: In a plural unit system, particularly of the data processing type, controlled units such as tape drives, constitute status reporting units (SRUs) which report status including error conditions to one or more status analyzing units such as computers (CPUs), programmable controllers, and the like. Each of the SRUs has a register, such as a shift register, associated therewith for receiving error status indications. The signal state of the shift register when all zeros indicates error-free status, any nonzero state signifies an error. An OR circuit receives signals from all of the bit positions of each of the respective shift registers and combines same into an SRU group error indicating signal. A second register, also a shift register, associated with the respective SRUs receives the output of the OR circuit in one of its bit positions, the bit position indicating the address of the reporting SRU. The output of the two shift registers associated with each of the SRUs are serialized onto one wire and supplied to an intermediate shift register. Combined signal status in the intermediate shift register are then supplied to one or more status analyzing units in a two byte format, i.e., one byte for the address and a second byte for the error status. An appropriate status analyzing unit then determines the error condition of the SRU. If more than one SRU is in error, then the address byte will have more than one binary one indicating state requiring further analysis by the respective status analyzing units.