公开(公告)号：CA1271269A

公开(公告)日：1990-07-03

申请号：CA562613

申请日：1988-03-28

Applicant: IBM

Inventor： BALASUBRAMANYAM KARANAM ,  JOSEPH ROBERT R ,  RENBECK ROBERT B

IPC: H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/338 ,  H01L29/47 ,  H01L29/812 ,  H01L29/64 ,  H01L21/00

Abstract: Disclosed is a novel MESFET having a gate which is of submicron length, planar and provided with submicron sidewall insulator spacers. The source and drain are very shallow and are self-aligned to the gate via the spacers. The device is endowed with minimal gate overlap capacitance since the gate has little lapping over the source/drain contact metal and the associated passivation dielectric. Disclosed too is a process of fabrication of the MESFET in which starting with a GaAs substrate having a shallow N- layer covered with nitride, a submicronwide gate consisting of upper and lower portions made of dissimilar materials is formed. Multilayer organic and sidewall image transfer techniques are employed for forming the mask. The nitride is etched using the gate mask. N+ source/drain are formed by ion implantation. The lower portion of the gate mask is etched to expose the periphery of the nitride. Refractory metal for source/drain contacts is deposited. An oxide layer is deposited to passivate the source/drain contacts and to fully cover the exposed nitride periphery. The gate mask is removed. High temperature anneal is accomplished to simultaneously activate the N+ regions and anneal the contact metal. By RIE the exposed nitride removed leaving submicron spacers thereof. Gate metal is deposited in the gate region. Excess gate metal is removed to obtain a gate which has a planar top and has little lapping over the source/drain contacts.