公开(公告)号：CA1244145A

公开(公告)日：1988-11-01

申请号：CA529470

申请日：1987-02-11

Applicant: IBM

Inventor： BALASUBRAMANYAM KARANAM ,  DALLY ANTHONY J ,  RISEMAN JACOB ,  OGURA SEIKI

IPC: H01L21/3205 ,  G03F7/09 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/72

Abstract: Disclosed is a process of forming high density, planar, single- or multi-level wiring for an semiconductor integrated circuit chip. On the chip surface is provided a dual layer of an insulator and hardened photoresist having various sized openings (grooves for wiring and openings for contacts) therein in a pattern of the desired wiring. A conductive (e.g., metal) layer of a thickness equal to that o. the insulator is deposited filling the grooves and contact openings. A sacrificial dual (lower and upper component) layer of (hardened) photoresist is formed filling the metal valleys and obtaining a substantially planar surface. The lower component layer is thin and conformal and has a higher etch rate than the upper component layer which is thick and nonconformal. By reactive ion etching the sacrificial layer is removed leaving resist plugs in the metal valleys. Using the plug as etch masks, the exposed metal is removed followed by removal of the remaining hardened photoresist layer and the plugs leaving a metal pattern coplanar with the insulator layer. This sequence of steps is repeated for multilevel wiring. When only narrow wiring is desired, a single photoresist layer is substituted for the dual photoresist sacrificial layer.

公开(公告)号：CA1271269A

公开(公告)日：1990-07-03

申请号：CA562613

申请日：1988-03-28

Applicant: IBM

Inventor： BALASUBRAMANYAM KARANAM ,  JOSEPH ROBERT R ,  RENBECK ROBERT B

IPC: H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/338 ,  H01L29/47 ,  H01L29/812 ,  H01L29/64 ,  H01L21/00

Abstract: Disclosed is a novel MESFET having a gate which is of submicron length, planar and provided with submicron sidewall insulator spacers. The source and drain are very shallow and are self-aligned to the gate via the spacers. The device is endowed with minimal gate overlap capacitance since the gate has little lapping over the source/drain contact metal and the associated passivation dielectric. Disclosed too is a process of fabrication of the MESFET in which starting with a GaAs substrate having a shallow N- layer covered with nitride, a submicronwide gate consisting of upper and lower portions made of dissimilar materials is formed. Multilayer organic and sidewall image transfer techniques are employed for forming the mask. The nitride is etched using the gate mask. N+ source/drain are formed by ion implantation. The lower portion of the gate mask is etched to expose the periphery of the nitride. Refractory metal for source/drain contacts is deposited. An oxide layer is deposited to passivate the source/drain contacts and to fully cover the exposed nitride periphery. The gate mask is removed. High temperature anneal is accomplished to simultaneously activate the N+ regions and anneal the contact metal. By RIE the exposed nitride removed leaving submicron spacers thereof. Gate metal is deposited in the gate region. Excess gate metal is removed to obtain a gate which has a planar top and has little lapping over the source/drain contacts.

公开(公告)号：SG68635A1

公开(公告)日：1999-11-16

申请号：SG1997003565

申请日：1997-09-25

Applicant: IBM

Inventor： BALASUBRAMANYAM KARANAM ,  BRODSKY STEPHEN BRUCE ,  CONTI RICHARD ANTHONY ,  EL-KAREH BADIH

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/43 ,  H01L29/78

Abstract: A MOSFET device is formed on a P- doped semiconductor substrate with an N- well formed therein, with a pair of isolation regions formed in the N- well with a gate oxide layer formed above the N- well. An FET device is formed with source and drain regions within the N-well, and a gate electrode formed above the gate oxide layer aligned with the source and drain regions. The gate electrode comprises a stack of layers. A polysilicon layer is formed on the gate oxide layer. A tungsten nitride dopant barrier layer is formed upon the polysilicon layer having a thickness of from about 5 nm to about 20 nm, and a tungsten silicide layer is formed upon the tungsten nitride layer.

公开(公告)号：DE3766737D1

公开(公告)日：1991-01-31

申请号：DE3766737

申请日：1987-02-11

Applicant: IBM

Inventor： BALASUBRAMANYAM KARANAM ,  RISEMAN JACOB ,  DALLY ANTHONY JOHN ,  OGURA SEIKI

IPC: H01L21/3205 ,  G03F7/09 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/90 ,  G03F7/26

Abstract: Disclosed is a process of forming high density, planar, single- or multi-level wiring for an semiconductor integrated circuit chip. On the chip surface (10) is provided a dual layer of an insulator (14) and hardened photoresist (16) having various sized openings (grooves for wiring and openings for contacts) therein in a pattern of the desired wiring. A conductive (e.g., metal) layer (22) of a thickness equal to that of the insulator is deposited filling the grooves and contact openings. A sacrificial dual (lower and upper component) layer of (hardened) photoresist (28, 30) is formed filling the metal valleys and obtaining a substantially planar surface (32). The lower component layer (28) is thin and conformal and has a higher etch rate than the upper component layer (30) which is thick and nonconformal. By reactive ion etching the sacrificial layer is removed leaving resist plugs in the metal valleys. Using the plug as etch masks, the exposed metal is removed followed by removal of the remaining hardened photo-resist layer and the plugs leaving a metal pattern coplanar with the insulator layer. This sequence of steps is repeated for multilevel wiring. When only narrow wiring is desired, a single photoresist layer is substituted for the dual photo-resist sacrificial layer.