公开(公告)号：EP1128427A8

公开(公告)日：2001-11-28

申请号：EP01301600

申请日：2001-02-22

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM ,  TOSHIBA KK

Inventor： DIVAKARUNI RUNI ,  LA ROSA GIUSEPPE ,  WEYBRIGHT MARY E ,  KATSUMATA RYOTA ,  RENGARAJAN RAJESH

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L21/823878 ,  H01L21/26506 ,  H01L21/28123 ,  H01L21/823481 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/7838

Abstract: P-type metal-oxide semiconductor field effect transistor (PMOSFET) devices have a characteristic property known as threshold voltage. This threshold voltage may consist of separate threshold voltages associated with the main portion of the gate region of the device and with the sidewall corner of the device. Under some conditions, the threshold behavior in the sidewall corner region of the device may dominate the performance of the device, not necessarily in the manner intended by the designer of the device. A method of controlling threshold voltage behavior is described. In particular, ion implantation of nitrogen in the gate sidewall region of the device can provide such control. Devices made by this method are also described.

公开(公告)号：WO2006057645A8

公开(公告)日：2006-08-03

申请号：PCT/US2004042179

申请日：2004-12-15

Applicant: IBM ,  CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

Inventor： CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

IPC: H01L29/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/109

CPC classification number: H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a -containing layer having a 110 crystal orientation and a biaxial compressive strain. The term ''biaxial compressive stress'' is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing 110 layer; and creating a biaxial strain in the silicon-containing 110 layer.

Abstract translation: 本发明提供具有增强的电子和空穴迁移率的半导体材料，其包含具有110晶向和双向压缩应变的含有层。 术语“双轴压缩应力”在本文中用于描述由在制造半导体材料期间在含Si层上感应的纵向压缩应力和横向应力引起的净应力。 本发明的另一方面涉及一种形成本发明的半导体材料的方法。 本发明的方法包括提供含硅110层的步骤; 并在含硅110层中产生双轴应变。

公开(公告)号：JP2001068672A

公开(公告)日：2001-03-16

申请号：JP2000210075

申请日：2000-07-11

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： DIVAKARUNI RAMA ,  JEFFREY P GANBINO ,  MANDELMAN JACK A ,  RENGARAJAN RAJESH

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To obtain an improved structure and a production process of semiconductor device, e.g. MOSFET, in which possibility of thermal shrinkage and permeation of boron are reduced. SOLUTION: A sacrificial oxide layer 1 and a polysilicon/silicon nitride film are deposited sequentially on a substrate 2, an opening is made therein by etching (at the part of 5, 15) and ions are implanted in order to suppress hot carriers 11 thus suppressing punch through 8 between source and drain. After it is filled with a gate insulation film 12, a polysilicon layer 14 and a tungsten layer 15, upper part of an implanted part 18 for extending the source-drain is opened by etching, a spacer 19 is formed therein and contact implantation appropriate to P or N type is carried out. Thereafter, a nitride etch barrier layer 20 is formed, a contact region 21 is opened and filled with a polysilicon layer 22.

公开(公告)号：JP2000040797A

公开(公告)日：2000-02-08

申请号：JP17017799

申请日：1999-06-16

Applicant: SIEMENS AG ,  IBM ,  TOSHIBA CORP

Inventor： RENGARAJAN RAJESH ,  INOUE HIROFUMI ,  SRINIVASAN RADHIKA ,  BEINTNER JOCHEN

IPC: H01L21/76 ,  H01L21/762 ,  H01L27/08

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming semiconductor elements, which are electrically insulated from each other within a silicon base body, and a semiconductor structure manufactured by this method. SOLUTION: This method of forming semiconductor elements is executed by having trenches formed in the selected regions of a silicon base body 10 and depositing a barrier material on the sidewalls of the trenches. The barrier material is removed from the first sidewall parts 34 of the trenches, while the barrier material is left on the second sidewall parts 32 of the trenches and a barrier layer 26 is formed in each trench. A dielectric material 38 is deposited in the trenches and the dielectric material is deposited on each of the exposed first sidewall parts within the trenches and the barrier layers within the trenches. The dielectric material is annealed in an oxidizing atmosphere and is highly compacted, and the second sidewall parts of the trenches are prevented from being oxidized by the barrier layers. A plurality of the semiconductor elements are formed within the silicon base body, and the elements are electrically insulated from each other by the dielectric material.

公开(公告)号：JP2003008013A

公开(公告)日：2003-01-10

申请号：JP2002136853

申请日：2002-05-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： AKATSU HIROYUKI ,  INABA SATOSHI ,  KATSUMATA RYOTA ,  MURTHY CHERUVU S ,  RENGARAJAN RAJESH ,  RONSHEIM PAUL A

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823481 ,  H01L21/823412

Abstract: PROBLEM TO BE SOLVED: To reduce the threshold voltage(Vt) roll-up/roll-off effect of a MOSFET.
SOLUTION: The MOSFET is formed through the stages of forming a 1st area by injecting a dopant of a 1st type into at least part of a semiconductor substrate, annealing the 1st well area, and injecting nitrogen into the annealed 1st well area; forming a gate insulating film on at least part of the 1st well area; and providing a gate electrode on a gate oxide film and providing a source/drain area on the substrate below the gate oxide film nearby the gate electrode.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：降低MOSFET的阈值电压（Vt）卷起/滚降效应。 解决方案：通过将第一类型的掺杂剂注入到半导体衬底的至少一部分中，使第一阱区域退火并将氮注入退火的第一阱区域中，形成第一区域的阶段; 在第一阱区的至少一部分上形成栅极绝缘膜; 以及在栅极氧化膜上提供栅极电极，并且在栅电极附近的栅极氧化膜下方的衬底上提供源极/漏极区域。

公开(公告)号：JP2000269441A

公开(公告)日：2000-09-29

申请号：JP29109099

申请日：1999-10-13

Applicant: IBM ,  SIEMENS AG

Inventor： JOACHIM HANS-OLIVER ,  MANDELMAN JACK A ,  RENGARAJAN RAJESH

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To reduce a swing below a threshold, a photoelectron degradation, and the sensitivity to a charge existing near the side wall of a device or the like, by forming a second divot shallower than a first divot in a region adjacent to an insulating P well. SOLUTION: This is a buried channel PFET device having a first deep divot 13 on the right side and a second shallow divot 12 on the left side. There is a gate conductor 14 of an N + polysilicon gate conductor and a p-type depletion layer 15 on an N well 11 surrounded by a nitride layer 16. A gate oxide layer 18 separates the gate conductor 14 from the depletion region 15. The nitride layer 16 contacts a shallow trench separation region 10. Contrary to an effect to a surface channel NFET, a parasitic conductance at the edge is produced by the shallow divot 12 in the buried channel PFET. If a gate control is out of control, a gradient below a threshold, an off current, and the reliability of a photoelectron are reduced.

公开(公告)号：WO2006057645A3

公开(公告)日：2006-11-30

申请号：PCT/US2004042179

申请日：2004-12-15

Applicant: IBM ,  CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

Inventor： CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

IPC: H01L29/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/109

CPC classification number: H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a -containing layer having a 110 crystal orientation and a biaxial compressive strain. The term ''biaxial compressive stress'' is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing 110 layer; and creating a biaxial strain in the silicon-containing 110 layer.

公开(公告)号：WO2006057645A9

公开(公告)日：2006-09-14

申请号：PCT/US2004042179

申请日：2004-12-15

Applicant: IBM ,  CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

Inventor： CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

IPC: H01L29/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/109

CPC classification number: H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a -containing layer having a 110 crystal orientation and a biaxial compressive strain. The term ''biaxial compressive stress'' is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing 110 layer; and creating a biaxial strain in the silicon-containing 110 layer.

公开(公告)号：DE102004016705A1

公开(公告)日：2004-11-25

申请号：DE102004016705

申请日：2004-04-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： YU CHIENFAN ,  RUPP THOMAS ,  DOBUZINSKI DAVID M ,  DEV PRAKASH C ,  RENGARAJAN RAJESH ,  NAEEM MUNIR-UD-DIN ,  BENEDICT JOHN ,  FALTERMEIER JOHNATHAN E ,  MALDEI MICHAEL

IPC: H01L21/311 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/283

Abstract: An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.

公开(公告)号：HK1032293A1

公开(公告)日：2001-07-13

申请号：HK01102845

申请日：2001-04-23

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： RAMA DIVAKARUNI ,  GAMBINO JEFFREY P ,  MANDELMAN JACK A ,  RENGARAJAN RAJESH

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78 ,  H01L

Abstract: The process rules for manufacturing semiconductor devices such as MOSFET's are modified to provide dual work-function doping following the customary gate sidewall oxidation step, greatly reducing thermal budget and boron penetration concerns. The concern of thermal budget is further significantly reduced by a device structure which allows a reduced gap aspect ratio while maintaining low sheet resistance values. A reduced gap aspect ratio also relaxes the need for highly reflowable dielectric materials and also facilitates the use of angled source-drain (S-D) and halo implants. Also provided is a novel structure and process for producing a MOSFET channel, lateral doping profile which suppresses short channel effects while providing low S-D junction capacitance and leakage, as well as immunity to hot-carrier effects. This also affords the potential for reduction in the contact stud-to-gate conductor capacitance, because borderless contacts can be formed with an oxide gate sidewall spacer. As a result, the S-D junctions can be doped independently of the gate conductor doping, more easily allowing a variety of MOSFET structures.