公开(公告)号：DE102004016705B4

公开(公告)日：2008-04-17

申请号：DE102004016705

申请日：2004-04-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： YU CHIENFAN ,  RUPP THOMAS ,  DOBUZINSKI DAVID M ,  DEV PRAKASH C ,  RENGARAJAN RAJESH ,  NAEEM MUNIR-UD-DIN ,  BENEDICT JOHN ,  FALTERMEIER JOHNATHAN E ,  MALDEI MICHAEL

IPC: H01L21/283 ,  H01L21/311 ,  H01L21/60 ,  H01L21/8239 ,  H01L21/8242 ,  H01L23/485 ,  H01L29/768

Abstract: An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.

公开(公告)号：DE102004016705A1

公开(公告)日：2004-11-25

申请号：DE102004016705

申请日：2004-04-05

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： YU CHIENFAN ,  RUPP THOMAS ,  DOBUZINSKI DAVID M ,  DEV PRAKASH C ,  RENGARAJAN RAJESH ,  NAEEM MUNIR-UD-DIN ,  BENEDICT JOHN ,  FALTERMEIER JOHNATHAN E ,  MALDEI MICHAEL

IPC: H01L21/311 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/283

Abstract: An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.

公开(公告)号：DE10240406A1

公开(公告)日：2003-06-05

申请号：DE10240406

申请日：2002-09-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHOLZ ARND ,  DEV PRAKASH C

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: A method is provided for forming an inside nitride spacer in a deep trench device DRAM cell. The method includes depositing an oxide liner in a trench etched from a semiconductor material, wherein the oxide lines abuts a pad nitride layer, a pad oxide layer under the pad nitride layer, and a recessed gate poly in the trench. The method further includes depositing a spacer material on the oxide liner, removing exposed portions of the oxide layer from the semiconductor, and depositing a poly stud material over the semiconductor wherein the spacer material is encapsulated in poly stud material. The method includes polishing the semiconductor to the top trench oxide layer, and etching the top trench oxide layer.