公开(公告)号：JPH0653495A

公开(公告)日：1994-02-25

申请号：JP13051793

申请日：1993-06-01

Applicant: IBM

Inventor： FUERUNANDO DOORIINZU ,  RIANNCHIYUU FUSHIA ,  RUISU ERUUSHII SHIYUU ,  JIERARUDO AARU RAASEN ,  JIERARUDEIN SHII SHIYUWARUTSU

IPC: H01L29/43 ,  H01L21/225 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/78 ,  H01L29/784 ,  H01L29/46

Abstract: PURPOSE: To provide a method of manufacturing an MOS transistor, having an inverted T-shaped high-m.p. metal gate. CONSTITUTION: This gate comprises a main CVD W layer 14A and lower sputtered W layer 16A, extending from the bottom of a CVD part to the outside, so that the gate section becomes like an inverted T-shape. To etch the CVD W layer, a Cl2 /O2 plasma etching is used. To etch the sputtered W layer for forming gate electrodes, a chemical etching is used. The sputtered W is etched to a lesser degree by the Cl2 /O2 reactive plasma etching than by the CVD W. The sputtered W layer acts as a shield to prevent a lower oxide layer 10 from the ion damages during manufacturing.