公开(公告)号：JP2003273235A

公开(公告)日：2003-09-26

申请号：JP2003053740

申请日：2003-02-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： MANDELMAN JACK A ,  FILIPPI RONALD G ,  JEFFREY P GANBINO ,  RICHARD A WAKNICK

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/60 ,  H01L21/822 ,  H01L23/522 ,  H01L23/528 ,  H01L27/04 ,  H01L27/08

CPC classification number: H01L21/76897 ,  H01L23/5222 ,  H01L23/5228 ,  H01L23/5286 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/82 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with interconnected conductor lines.
SOLUTION: The semiconductor device includes a lower Interlayer Dielectric (ILD) layer having a top surface formed on a substrate. Several lower conductor lines surrounded by an insulator formed on the lower ILD layer are formed on the top surface of the lower ILD layer. Each of a set of resistive studs has sidewalls, a lower end and an upper end and the set is joined to the top of the lower conductor line at the lower end. There are several intermediate conductor lines formed between the resistive studs separated from adjacent studs by a liner layer and a capacitor dielectric layer. Upper conductor lines are formed on an upper level. Each of the upper conductor lines has a bottom surface in contact with a corresponding one of the resistive studs. A central ILD layer overlies the intermediate conductor for electrically insulating and separating the intermediate conductor lines from the upper conductor lines.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供配备有互连的导线的半导体器件。 解决方案：半导体器件包括具有形成在衬底上的顶表面的下层间介电层（ILD）层。 在下部ILD层的上表面形成有由下部ILD层形成的绝缘体围绕的多个下部导体线。 一组电阻螺柱中的每一个具有侧壁，下端和上端，并且该组在下端处连接到下导体线的顶部。 在通过衬垫层和电容器电介质层从相邻螺柱分离的电阻螺柱之间形成几个中间导体线。 上导线形成在上层。 每个上导体线具有与相应的一个电阻螺柱接触的底表面。 中间ILD层覆盖中间导体，用于将中间导体线与上导体线电绝缘和分离。 版权所有（C）2003，JPO

公开(公告)号：JPH1174268A

公开(公告)日：1999-03-16

申请号：JP19306398

申请日：1998-07-08

Applicant: IBM

Inventor： FILIPPI RONALD G ,  RICHARD A WAKNICK

IPC: H01L23/52 ,  H01L21/3205 ,  H01L23/528 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device having a multilevel wiring structure, which is provided with alternate metallization interconnection and an insulating passivation layer. SOLUTION: A normal width line metallization interconnecting conductive line 70, which is surrounded by an insulating passivation layer, is replaced with two or more narrow-width parallel conductive lines 71, having an aspect ratio of 1 or less (a passivation layer 77 is provided between the lines), and passivation crackings and push-out short circuit failures are reduced. This method is specially applicable to a multilevel interconnection structure. In the multilevel interconnection structure, the wiring level is provided with a diffused barrier between the wiring levels, which is generated by an added metallization layer and interlevel connection or by both.