中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.019 seconds)

    METALLIZATION STRUCTURE
    2.
    发明专利
    METALLIZATION STRUCTURE 失效

    公开(公告)号：JPH10308362A

    公开(公告)日：1998-11-17

    申请号：JP11245598

    申请日：1998-04-22

    Applicant: IBM ,  TOSHIBA CORP

    Inventor： USUI TAKAMASA ,  DEHAVEN PATRICK W ,  RODBELL KENNETH P ,  FILIPPI RONALD G

    IPC: C23C14/14 ,  C23C16/06 ,  C23C28/02 ,  H01L21/28 ,  H01L21/285

    Abstract: PROBLEM TO BE SOLVED: To provide a metallization structure, which is small in resistivity, has excellent electricity transfer characteristics and at the same time, is textured to a high degree, and moreover, to prevent the formation of a hillock on the structure by a method wherein aluminium layers, aluminium alloy layers or both layers of the aluminium layers and the aluminum alloy layers, which come into contact electrically with tower group IVA metal layers having a thickness in a specified range, are formed. SOLUTION: Four or five-layer interconnected metallized layers are formed on interlayer stud connection layers 10, which are encircled with an insulator 8 and are connected with a silicon substratelike device substrate 6. Lower group IVA metal layers 13 consist of a titanium layer and the thickness of a metallization structure is about 90 to about 110 angstroms. By limiting this thickness, the structure of a metal layer, which is added afterwards, and the texture of the metal layer are controlled. Layers 15 to come into contact electrically with the lower layers 13 are aluminium layers or aluminium alloy layers. Titanium nitride layers 14 on the lower layers 13 prevent a reaction of the aluminium layers 15 with the lower layers 13 and capping layers consisting of titanium layers 18 and titanium nitride layers 19 perform an antireflection action.

    INTEGRATED CIRCUIT
    3.
    发明专利
    INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH11330244A

    公开(公告)日：1999-11-30

    申请号：JP9247299

    申请日：1999-03-31

    Applicant: SIEMENS AG ,  IBM

    Inventor： CLEVENGER LAWRENCE A ,  FILIPPI RONALD G ,  HOINKIS MARK ,  HURD JEFFERY L ,  IGGULDEN ROY C ,  PALM HERBERT ,  POETZLBERGER HANS W ,  RODBELL KENNETH P ,  SCHNABEL FLORIAN ,  WEBER STEFAN ,  MEHTER EBRAHIM A

    IPC: H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

    Abstract: PROBLEM TO BE SOLVED: To provide an interconnection with a damascene structure having an improved reliability, by using a liner for surrounding or sealing a conductor to give random crystal grain orientation to a conductive material. SOLUTION: A layer 137 is deposited on an insulating layer 130. A layer for lining the wall and the bottom of the contact opening functions as a base coat or liner for a conductive layer 138 to be subsequently deposited to fill the contact opening, and the degree of crystal grain orientation randomness of a material that fills the damascene structure is expanded. A parameter used for depositing a TiN layer is selected to expand the degree of base coat crystal grain orientation randomness and/or amorphous characteristics. The liner has an enough thickness to ensure the random crystal grain orientation of the conductive material to be subsequently deposited. Thus, the interconnection in an IC having the improved reliability can be obtained.

    Semiconductor device and method for forming the same
    6.
    发明专利
    Semiconductor device and method for forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：JP2003273235A

    公开(公告)日：2003-09-26

    申请号：JP2003053740

    申请日：2003-02-28

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： MANDELMAN JACK A ,  FILIPPI RONALD G ,  JEFFREY P GANBINO ,  RICHARD A WAKNICK

    IPC: H01L21/768 ,  H01L21/02 ,  H01L21/60 ,  H01L21/822 ,  H01L23/522 ,  H01L23/528 ,  H01L27/04 ,  H01L27/08

    CPC classification number: H01L21/76897 ,  H01L23/5222 ,  H01L23/5228 ,  H01L23/5286 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/82 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device equipped with interconnected conductor lines.
    SOLUTION: The semiconductor device includes a lower Interlayer Dielectric (ILD) layer having a top surface formed on a substrate. Several lower conductor lines surrounded by an insulator formed on the lower ILD layer are formed on the top surface of the lower ILD layer. Each of a set of resistive studs has sidewalls, a lower end and an upper end and the set is joined to the top of the lower conductor line at the lower end. There are several intermediate conductor lines formed between the resistive studs separated from adjacent studs by a liner layer and a capacitor dielectric layer. Upper conductor lines are formed on an upper level. Each of the upper conductor lines has a bottom surface in contact with a corresponding one of the resistive studs. A central ILD layer overlies the intermediate conductor for electrically insulating and separating the intermediate conductor lines from the upper conductor lines.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题：提供配备有互连的导线的半导体器件。 解决方案：半导体器件包括具有形成在衬底上的顶表面的下层间介电层（ILD）层。 在下部ILD层的上表面形成有由下部ILD层形成的绝缘体围绕的多个下部导体线。 一组电阻螺柱中的每一个具有侧壁，下端和上端，并且该组在下端处连接到下导体线的顶部。 在通过衬垫层和电容器电介质层从相邻螺柱分离的电阻螺柱之间形成几个中间导体线。 上导线形成在上层。 每个上导体线具有与相应的一个电阻螺柱接触的底表面。 中间ILD层覆盖中间导体，用于将中间导体线与上导体线电绝缘和分离。 版权所有（C）2003，JPO

    INTEGRATED CIRCUIT AND ITS MANUFACTURE
    7.
    发明专利
    INTEGRATED CIRCUIT AND ITS MANUFACTURE 失效

    公开(公告)号：JPH1174268A

    公开(公告)日：1999-03-16

    申请号：JP19306398

    申请日：1998-07-08

    Applicant: IBM

    Inventor： FILIPPI RONALD G ,  RICHARD A WAKNICK

    IPC: H01L23/52 ,  H01L21/3205 ,  H01L23/528 ,  H01L23/532

    Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device having a multilevel wiring structure, which is provided with alternate metallization interconnection and an insulating passivation layer. SOLUTION: A normal width line metallization interconnecting conductive line 70, which is surrounded by an insulating passivation layer, is replaced with two or more narrow-width parallel conductive lines 71, having an aspect ratio of 1 or less (a passivation layer 77 is provided between the lines), and passivation crackings and push-out short circuit failures are reduced. This method is specially applicable to a multilevel interconnection structure. In the multilevel interconnection structure, the wiring level is provided with a diffused barrier between the wiring levels, which is generated by an added metallization layer and interlevel connection or by both.

Patent Agency Ranking