Abstract:
A METHOD OF PARTIALLY PLANARIZING AN ELECTRICALLY INSULATIVE LAYER OVER AN INTEGRATED CIRCUIT SUBSTRATE WHICH HAS A RAISED LINE METALLIZATION PATTERN HAVING NARROWER LINES AND WIDER LINES. THE INSULATIVE LAYER HAS NARROWER AND WIDER ELEVATIONS CORRESPONDING TO THE UNDERLYING LINES. RESPUTTERING OF SAID INSULATIVE LAYER IS CONDUCTED FOR AN AMOUNT OF TIME SUFFICIENT TO SO PLANARIZE ITS WIDER TIONS IN THE LAYER BUT INSUFFICIENT TO SO PLANARIZE ITS WIDER ELEVATIONS. THIS METHOD IS USEFUL IN PLANARIZING INSULATIVE LAYER ELEVATIONS THROUGH WHICH VIA HOLES ARE TO BE FORMED, PARTICULARLY VIA HOLES WHICH ARE WIDER THAN THE UNDERLYING METALLIZING LINES WHICH THEY CONTACT. SUCH A PLANARIZATION METHOD IN VIA HOLE FORMATION AVOIDS THE TUNNELING EFFECTS WHICH WOULD OTHERWISE RESULT FROM THE OVER-CHEMICAL ETCHING NECESSARY TO FORM THE VIA HOLES.