公开(公告)号：JP2004119970A

公开(公告)日：2004-04-15

申请号：JP2003305482

申请日：2003-08-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MISEWICH JAMES A ,  REOHR WILLIAM ROBERT ,  SCHROTT ALEJANDRO GABRIEL ,  RIIKON WAN

IPC: G11C11/22 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L21/28291 ,  H01L27/11507 ,  H01L27/11585 ,  H01L27/1159 ,  H01L29/6684 ,  H01L29/78391

Abstract: PROBLEM TO BE SOLVED: To provide a ferroelectric gate field-effect tranisistor and a nonvolatile memory architecture, formed using it. SOLUTION: A vertical ferroelectric gate field-effect transistor (FeGFET) is provided with a substrate and a first drain/source electrode formed on the top surface of the substrate. A conductive channel region is formed on the top surface of the first drain/source electrode, and electrically connected to it. The FeGFET device is further provided with a ferroelectric gate region formed on at least one sidewall of the channel region, at least one gate electrode electrically contacting the ferroelectric gate region, and a second drain/source electrode, formed on the top surface of the channel region and electrically contacts the channel region. The ferroelectric gate region can be selectively polarized, depending on the potential supplied between the gate electrode and at least one of first and second drain/source electrode. A nonvolatile memory array, provided with a plurality of FeGFET device, is formed. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2002117676A

公开(公告)日：2002-04-19

申请号：JP2001193378

申请日：2001-06-26

Applicant: IBM

Inventor： LOUIS L SHEW ,  RIIKON WAN

IPC: G11C11/413 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/4076 ,  H01L21/822 ,  H01L27/04 ,  H02M3/07

Abstract: PROBLEM TO BE SOLVED: To provide a voltage control system and a method for keeping a voltage level generated inside a semiconductor chip. SOLUTION: The method comprises a step, in which the internal voltage supply level is sampled intermittently in a low electric power mode or a 'sleep' mode, a step in which the internal voltage supply level is compared with a prescribed voltage reference level, and a step in which a voltage supply generator is activated, when an internal voltage supply level is dropped to a level being less than the prescribed voltage reference level and the internal voltage supply level is raised. When the voltage supply level is restored to the prescribed voltage reference level, the voltage supply generator is made inactive. A sampling cycle can be adjusted appropriately according to chip conditions, chip temperature, and chip size. In one embodiment, the voltage control system and the method are performed by a DRAM circuit at refresh-operation. A voltage level, including band gap reference voltage of a DRAM, line voltage for boosted word lines, LOW voltage for word lines, HIGH voltage for bit lines, and bit line equalizing voltage is suitable for sampling.

公开(公告)号：JP2003007062A

公开(公告)日：2003-01-10

申请号：JP2002182086

申请日：2002-06-21

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： HSU LOUIS ,  RIIKON WAN

IPC: G11C11/408 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/406 ,  G11C11/4076

CPC classification number: G11C8/12 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/4076

Abstract: PROBLEM TO BE SOLVED: To provide a decoding system for performing a plurality of pieces of operation for the semiconductor memory device of a stack bank type.
SOLUTION: A decoding unit is provided to a memory bank group provided with a plurality of memory banks. When a reading and writing bank address coincides with two different memory banks in the same memory bank group, the decoding unit receives a reading and writing address and generates two different row selection signals for reading and writing operation in the two different banks. Based on the row selection signal, row decoder units in the two coincident banks simultaneously activate a target row designated by the reading and writing address.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种用于对堆叠类型的半导体存储器件执行多个操作的解码系统。 解决方案：解码单元提供给设置有多个存储体的存储体组。 当读取和写入存储体地址与同一存储体组中的两个不同的存储体一致时，解码单元接收读取和写入地址，并在两个不同的存储体中产生用于读取和写入操作的两个不同的行选择信号。 基于行选择信号，两个重合行中的行解码器单元同时激活由读取和写入地址指定的目标行。

公开(公告)号：JPH06314790A

公开(公告)日：1994-11-08

申请号：JP5010894

申请日：1994-03-22

Applicant: IBM

Inventor： UEN SHIN CHIYAN ,  RIIKON WAN

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762 ,  H01L29/786 ,  H01L29/784

Abstract: PURPOSE: To provide an FET structure in which roll-off of threshold voltage of a short channel is improved, and leakage currents of a source channel and a drain channel are reduced. CONSTITUTION: An FET 34 composed of a source area 36, a channel area 40, and a drain area 38 is manufactured on a semiconductor material substrate 24 provided on an upper side of an insulating layer formed further on an upper surface of a semiconductor material base substrate 10. A gate area 42 is provided further on the FET 34 which is located on the channel 40 and is separated from the same. The base substrate 10 includes a mesa area 18 extending to an insulating layer located below the channel 40 so that the base substrate 10 more approaches the channel 40 than areas of the source 36 and drain 38 do. Thus, the channel 40 is shielded from source and drain voltages and hence the influence is reduced from them.