公开(公告)号：JPH04232688A

公开(公告)日：1992-08-20

申请号：JP21940791

申请日：1991-08-06

Applicant: IBM

Inventor： SANGU FUU DONGU ,  ROBAATO ROISU FURANCHI ,  UEI UANGU

IPC: G11C11/401 ,  G11C11/406 ,  G11C29/00 ,  G11C29/04

Abstract: PURPOSE: To prolong refresh interval by replacing a DRAM cell of a short data hold time with a redundant static memory cell. CONSTITUTION: Charges stored in capacity in the DRAM cell are discharged to an allowable level or below after a prescribed time interval T1 in many cells, and are discharged to the allowable level or below after a shorter time interval T2 in few cells. The refresh cycle of the DRAM is adjusted so as to become longer than the T2. This DRAM circuit contains plural redundant storage cells 50, a decoder receiving the addresses of the cells and a switch circuit. The decoder generates a first output when the receiving address is the address of the many cells, and generates a second output when the receiving address is the address of the few cells. The switch circuit allows to access the redundant storage cell in response to the first output to block the access of the few cells.