公开(公告)号：JPH08340095A

公开(公告)日：1996-12-24

申请号：JP13220196

申请日：1996-05-27

Applicant: IBM

Inventor： SEIKI OGURA ,  NIBO ROBEDO ,  ROBAATO SHII UON

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a process for manufacturing a high-density memory array. SOLUTION: N-type impurities are implanted in a P-type substrate, and continuous diffused rails 24, which have a substantially flat outline, are formed. A bit line, which corresponds to each rail 24, is specified by the rail 24. Source and drain regions of each adjacent memory array cell pair, which is related with each bit line, are specified by each rail. In one mode, a plurality of polysilicon layers are used for forming control gates, a floating gate 18, sources and drains. The polysilicon layers are self-aligned with each other, so as to substantially reduce an overlapping of the polysilicon layers for minimizing the parasitic capacitance of a memory array. Domino and and skippy domino mechanisms are used for programming a memory array cell and for reading out the programming. A comparatively low programming voltage is used for the programming, and the programming is realized by a channel hot electron tunneling phenomenon.