公开(公告)号：JP2006331630A

公开(公告)日：2006-12-07

申请号：JP2006142478

申请日：2006-05-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ELEFTHERIOU EVANGELOS S ,  ROBERT A HUTCHINS ,  OELCER SEDAT

IPC: G11B20/10 ,  G11B5/09

CPC classification number: G11B5/09 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10481 ,  G11B2005/0013 ,  G11B2220/90

Abstract: PROBLEM TO BE SOLVED: To provide a method for an equalizer calculation in a media system using a data set separator sequence.
SOLUTION: An equalizer coefficient generator receives a DSS (data set separator)sequence and a DSS readback sequence being a function of channel processing of the DSS sequence by a read channel. The generator generates a coefficient cyclic equalizer vector as a function of the DSS sequence and DSS readback sequence. Furthermore, the generator generates an error signal as a function for comparing the DSS sequence with the DSS readback sequence based on the coefficient cyclic equalizer vector in equalization. An unacceptable error signal shows the need of adjusting the coefficient cyclic equalizer vector so as to obtain acceptable comparison of the DSS sequence with the DSS readback sequence based on the coefficient cyclic equalizer vector in equalization.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种使用数据集分离器序列在媒体系统中进行均衡器计算的方法。 解决方案：均衡器系数生成器接收DSS（数据集分离器）序列，DSS回读序列是读通道对DSS序列的通道处理的函数。 发生器产生作为DSS序列和DSS回读序列的函数的系数循环均衡器向量。 此外，发生器产生误差信号作为用于基于均衡中的系数循环均衡器向量来比较DSS序列与DSS回读序列的函数。 不可接受的误差信号表示需要调整系数循环均衡器向量，以便基于均衡中的系数循环均衡器向量来获得DSS序列与DSS回读序列的可接受的比较。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：GB2533501B

公开(公告)日：2018-01-10

申请号：GB201603366

申请日：2014-07-28

Applicant: IBM

Inventor： ROY D CIDECIYAN ,  ROBERT A HUTCHINS ,  THOMAS MITTELHOLZER ,  KEISUKE TANAKA

IPC: H03M13/29 ,  H03M13/15 ,  H03M13/37

Abstract: In one embodiment, a method for combination error and erasure decoding for product codes includes receiving, using a hardware processor, captured data. The method also includes generating, using the hardware processor, erasure flags for the captured data and providing the erasure flags to a C2 decoder. Moreover, the method includes setting a stop parameter to be equal to a length of C1 codewords in a codeword interleave used to encode the captured data. In addition, the method includes selectively performing, in an iterative process, error or erasure C1 decoding followed by error or erasure C2 decoding until decoding is successful or unsuccessful. Other methods and computer program products are described in more embodiments.

公开(公告)号：GB2515921B

公开(公告)日：2020-03-18

申请号：GB201414771

申请日：2013-03-20

Applicant: IBM

Inventor： ROY DARON CIDECIYAN ,  ROBERT A HUTCHINS ,  THOMAS MITTELHOLZER ,  SEDAT OELCER

IPC: H03M5/14 ,  H03M13/11 ,  H03M13/29 ,  H03M13/39

公开(公告)号：GB2533501A

公开(公告)日：2016-06-22

申请号：GB201603366

申请日：2014-07-28

Applicant: IBM

Inventor： ROY D CIDECIYAN ,  ROBERT A HUTCHINS ,  THOMAS MITTELHOLZER ,  KEISUKE TANAKA

IPC: H03M13/29 ,  H03M13/15 ,  H03M13/37

Abstract: In one embodiment, a system for combination error and erasure decoding for product codes includes a processor and logic integrated with and/or executable by the processor, the logic being configured to receive captured data, generate erasure flags for the captured data and provide the erasure flags to a C2 decoder, set a stop parameter to be equal to a length of C1 codewords in a codeword interleave used to encode the captured data, and selectively perform, in an iterative process, error or erasure C1 decoding followed by error or erasure C2 decoding until decoding is successful or unsuccessful. In more embodiments, a method and/or a computer program product may be used for combination error and erasure decoding for product codes.