公开(公告)号：GB2492708B

公开(公告)日：2017-01-25

申请号：GB201219123

申请日：2011-03-23

Applicant: IBM

Inventor： ROY D CIDECIYAN ,  EVANGELOS STAVROS ELEFTHERIOU ,  THOMAS MITTELHOLZER

IPC: G06F11/10 ,  H03M13/15 ,  H03M13/29

公开(公告)号：GB2533501A

公开(公告)日：2016-06-22

申请号：GB201603366

申请日：2014-07-28

Applicant: IBM

Inventor： ROY D CIDECIYAN ,  ROBERT A HUTCHINS ,  THOMAS MITTELHOLZER ,  KEISUKE TANAKA

IPC: H03M13/29 ,  H03M13/15 ,  H03M13/37

Abstract: In one embodiment, a system for combination error and erasure decoding for product codes includes a processor and logic integrated with and/or executable by the processor, the logic being configured to receive captured data, generate erasure flags for the captured data and provide the erasure flags to a C2 decoder, set a stop parameter to be equal to a length of C1 codewords in a codeword interleave used to encode the captured data, and selectively perform, in an iterative process, error or erasure C1 decoding followed by error or erasure C2 decoding until decoding is successful or unsuccessful. In more embodiments, a method and/or a computer program product may be used for combination error and erasure decoding for product codes.

公开(公告)号：GB2533501B

公开(公告)日：2018-01-10

申请号：GB201603366

申请日：2014-07-28

Applicant: IBM

Inventor： ROY D CIDECIYAN ,  ROBERT A HUTCHINS ,  THOMAS MITTELHOLZER ,  KEISUKE TANAKA

IPC: H03M13/29 ,  H03M13/15 ,  H03M13/37

Abstract: In one embodiment, a method for combination error and erasure decoding for product codes includes receiving, using a hardware processor, captured data. The method also includes generating, using the hardware processor, erasure flags for the captured data and providing the erasure flags to a C2 decoder. Moreover, the method includes setting a stop parameter to be equal to a length of C1 codewords in a codeword interleave used to encode the captured data. In addition, the method includes selectively performing, in an iterative process, error or erasure C1 decoding followed by error or erasure C2 decoding until decoding is successful or unsuccessful. Other methods and computer program products are described in more embodiments.

公开(公告)号：SG87129A1

公开(公告)日：2002-03-19

申请号：SG200003552

申请日：2000-06-24

Applicant: IBM

Inventor： ROY D CIDECIYAN ,  JONATHAN DARREL COKER ,  EVANGELOS STAVROS ELEFTHERIOU ,  RICHARD LEO GALBRAITH ,  TODD TRUAX

IPC: G11B20/14 ,  G11B20/18 ,  G06F11/10 ,  H03M5/14 ,  H03M7/14 ,  H03M7/42 ,  H03M13/01 ,  H03M13/05 ,  H03M13/31 ,  H04L1/00 ,  H04L25/49

Abstract: A method and apparatus for encoding a plurality of successive m-bit binary data words to produce a plurality of successive of n-bit binary code words, where n and m are positive integers and n is greater than m, for supply to a magnetic recording channel. Each m-bit binary data word is partitioned into a plurality of blocks of bits, and at least one said blocks of bits in each m-bit binary data word is encoded in accordance with a finite-state coding scheme to produce a plurality of successive n-bit binary code words. At least one stage of violation correction which transforms the plurality of successive n-bit binary code words. Violation correction includes detecting the occurrence of any of a plurality of prohibited bit patterns at one or more predetermined locations within each n-bit binary coded word, and replacing any prohibited bit pattern so detected by a corresponding substitute bit pattern. The finite-state coding scheme, the prohibited bit patterns, and corresponding substitute bit patterns are predetermined such that in a serial bit-steam comprising the successive n-bit binary code words, the maximum number of consecutive bits of a first value is limited to a first predetermined number j, where b greater or equal to 2, and the maximum number of consecutive bits of the a second value is limited to a second predetermined number k.