公开(公告)号：JPH10187552A

公开(公告)日：1998-07-21

申请号：JP27749997

申请日：1997-10-09

Applicant: IBM

Inventor： LATTIMORE GEORGE M ,  ROBERT P MASLEYD ,  JOHN S MUHICHI

IPC: G06F12/16 ,  G11C8/12 ,  G11C29/00 ,  G11C29/04

Abstract: PROBLEM TO BE SOLVED: To overcome a defect in a circuit of a semiconductor element by including memory cells and a word line decoder connected to only the memory cells in a redundant memory array. SOLUTION: A subarray 324 includes the word line decoder 202, the memory cells 204, a bit line decoder 206, and an input/output circuit 208. The word line decoder 202 is connected to the memory cells 204 and provides pieces of decoded data. Further, the bit line decoder 206 is connected to the memory cells 204 and communicates decoded data or data to be decoded. The input/ output circuit 208 is connected to the bit line decoder 206, which communicates data to the bit line decoder 206 to determine a value corresponding to the data. The subarray 324 has substantially the same structure with other subarrays which are shown here.