公开(公告)号：DE3785961D1

公开(公告)日：1993-07-01

申请号：DE3785961

申请日：1987-01-13

Applicant: IBM

Inventor： HUFFMAN DAVID RICHARD ,  LEWIS SCOTT CLARENCE ,  ROCK JAMES EDWARD

IPC: G11C11/56 ,  G11C27/02 ,  G11C7/00

Abstract: An improved sense circuit for determining the data state of a memory cell in a multilevel storage system includes at least two differential voltage level sensing circuits (13, 14). A first differential voltage level sensing circuit (13) compares the relative magnitudes of a data input signal voltage level corresponding to a particular memory cell (11 or 12) charge level and a first reference voltage level, thereby providing at least one first binary data output signal (D1). The first binary data output signal is then used to generate a second reference voltage level having a magnitude different from that of the first reference voltage level. A second differential voltage sensing level circuit (14) compares the relative magnitudes of an adjusted data input signal voltage level and a second reference voltage level, thereby providing at least one second binary data output signal (D2). The adjusted data input signal corresponds to a function of the first data input signal. Hence, the binary data output signals provided correspond to the charge level stored in the memory cell.

公开(公告)号：DE2659660A1

公开(公告)日：1977-09-29

申请号：DE2659660

申请日：1976-12-30

Applicant: IBM

Inventor： LEWIS SCOTT CLARENCE ,  REDMAN THEODORE MILTON ,  ROCK JAMES EDWARD ,  WILDER DONALD LAWRENCE

IPC: G11C11/417 ,  G11C7/00 ,  G11C11/34 ,  G11C11/4093 ,  G11C11/418 ,  H03K3/356 ,  H03K5/02

公开(公告)号：DE3785961T2

公开(公告)日：1993-12-23

申请号：DE3785961

申请日：1987-01-13

Applicant: IBM

Inventor： HUFFMAN DAVID RICHARD ,  LEWIS SCOTT CLARENCE ,  ROCK JAMES EDWARD

IPC: G11C11/56 ,  G11C27/02 ,  G11C7/00

Abstract: An improved sense circuit for determining the data state of a memory cell in a multilevel storage system includes at least two differential voltage level sensing circuits (13, 14). A first differential voltage level sensing circuit (13) compares the relative magnitudes of a data input signal voltage level corresponding to a particular memory cell (11 or 12) charge level and a first reference voltage level, thereby providing at least one first binary data output signal (D1). The first binary data output signal is then used to generate a second reference voltage level having a magnitude different from that of the first reference voltage level. A second differential voltage sensing level circuit (14) compares the relative magnitudes of an adjusted data input signal voltage level and a second reference voltage level, thereby providing at least one second binary data output signal (D2). The adjusted data input signal corresponds to a function of the first data input signal. Hence, the binary data output signals provided correspond to the charge level stored in the memory cell.