公开(公告)号：JP2002182974A

公开(公告)日：2002-06-28

申请号：JP2001311731

申请日：2001-10-09

Applicant: IBM

Inventor： ROGERS JIM L ,  FISCUS TIMOTHY E

IPC: G06F12/00 ,  G06F13/00 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407

Abstract: PROBLEM TO BE SOLVED: To perform read of a double data rate(DDR) DRAM at a data transfer rate being higher than that of the entire existing circuits which are using a strobe and a data protocol by realizing a circuit with mitigated relation between the strobe and a data eye and also a protocol. SOLUTION: A strobe generator 149 connected to both of a data input and a strobe input is added in order to control the multiple latch circuit 33 of a write circuit 118 so that a write circuit of conventional technique is changed. An initializing and validating circuit is connected and also a data comparing circuit which is connected between a storage array 21 and a toggle circuit is added in order to control the strobe so that a read circuit of conventional technique is changed. The strobe for reading/writing is generated only when a data state transition does not exist so that it is made unnecessary to perform positioning of the strobe and the data eye.

公开(公告)号：JPH10208471A

公开(公告)日：1998-08-07

申请号：JP28039197

申请日：1997-10-14

Applicant: IBM

Inventor： MILLER CHRISTOPHER P ,  ROGERS JIM L ,  TOMASHOT STEVEN W

IPC: G11C11/407 ,  G06F12/08 ,  G11C7/10 ,  G11C11/401

Abstract: PROBLEM TO BE SOLVED: To improve the performance of an SDRAM by a method wherein the waiting time of a memory is reduced and the simultaneous operations in a same memory bank is made to be performed. SOLUTION: In a cache synchronous dynamic random access memory(SDRAM) device having a multibank architecture, the rows of data latched by a sensing amplifier 106A are stored in a row register 102A which can be addressed at random. A selective logic gate means inputs the rows of data to the gate of the row register selectively in accordance with the specific implemented synchronous memory operation of the cache SDRAM 100. Data inputted to the cache SDRAM 100 during the writing operation are received by a sensing amplifier and written in a memory bank array. Data which are outputted from the cache SDRAM during the reading command are read out of a register 102A only.