公开(公告)号：JPH10208471A

公开(公告)日：1998-08-07

申请号：JP28039197

申请日：1997-10-14

Applicant: IBM

Inventor： MILLER CHRISTOPHER P ,  ROGERS JIM L ,  TOMASHOT STEVEN W

IPC: G11C11/407 ,  G06F12/08 ,  G11C7/10 ,  G11C11/401

Abstract: PROBLEM TO BE SOLVED: To improve the performance of an SDRAM by a method wherein the waiting time of a memory is reduced and the simultaneous operations in a same memory bank is made to be performed. SOLUTION: In a cache synchronous dynamic random access memory(SDRAM) device having a multibank architecture, the rows of data latched by a sensing amplifier 106A are stored in a row register 102A which can be addressed at random. A selective logic gate means inputs the rows of data to the gate of the row register selectively in accordance with the specific implemented synchronous memory operation of the cache SDRAM 100. Data inputted to the cache SDRAM 100 during the writing operation are received by a sensing amplifier and written in a memory bank array. Data which are outputted from the cache SDRAM during the reading command are read out of a register 102A only.

公开(公告)号：CA2026461A1

公开(公告)日：1991-06-06

申请号：CA2026461

申请日：1990-09-28

Applicant: IBM

Inventor： HILTEBEITEL NATHAN R ,  TAMLYN ROBERT ,  TOMASHOT STEVEN W

IPC: G11C11/401 ,  G11C11/4096

Abstract: A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells (10, 20). A first set of multiplexer devices (14, 24) selects one of the two pairs of folded bit lines from each of the arrays (10, 20), and a second set of multiplexer devices (16, 26) selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

公开(公告)号：CA2026461C

公开(公告)日：1993-03-09

申请号：CA2026461

申请日：1990-09-28

Applicant: IBM

Inventor： HILTEBEITEL NATHAN R ,  TAMLYN ROBERT ,  TOMASHOT STEVEN W

IPC: G11C11/401 ,  G11C11/4096 ,  G11C11/40 ,  G11C11/34 ,  G11C11/409

Abstract: MULTIPLEXED SERIAL REGISTER ARCHITECTURE FOR VRAM A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells. A first set of mux devices selects one of the two pairs of folded bit lines from each of the arrays, and a second set of mux devices selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

公开(公告)号：BR9006027A

公开(公告)日：1991-09-24

申请号：BR9006027

申请日：1990-11-28

Applicant: IBM

Inventor： HILTEBEITEL NATHAN R ,  TAMLYN ROBERT ,  TOMASHOT STEVEN W

IPC: G11C11/401 ,  G11C11/4096 ,  G11C15/00

Abstract: A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells (10, 20). A first set of multiplexer devices (14, 24) selects one of the two pairs of folded bit lines from each of the arrays (10, 20), and a second set of multiplexer devices (16, 26) selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.