公开(公告)号：JPH0492287A

公开(公告)日：1992-03-25

申请号：JP20831690

申请日：1990-08-08

Applicant: IBM

Inventor： KATAYAMA YASUNAO ,  KIRIHATA TOSHIAKI ,  ROI EDOUIN SHIYUWARAIRE

IPC: G11C11/409 ,  G11C11/4091

Abstract: PURPOSE: To realize a DRAM capable of high speed operation by limiting a downward voltage swing of a low level side bit line to a prescribed voltage level higher than a reference voltage. CONSTITUTION: The downward voltage swing of the low level side bit line BLN generating by the activation of a first latch 10 is made to clamp to a prescribed bit line voltage level by controlling the voltage of a common node N1 of the first latch 10. And when FETs TN5, TN6 are continued to conduct, the voltage of the low level side bit line is dropped to about zero V. Hear, when the voltage of the low level side bit line BLN is dropped to a prescribed bit line low voltage level VBLL corresponding to a low level restore voltage by the activation of the latch 10, a PS1 and PS2 become low to turn off the TN5 and TN6. Therefore, the low level restore voltage is automatically provided to the low level side bit line.