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    System and method for placing processor into gradually slow mode of operation
    2.
    发明专利
    System and method for placing processor into gradually slow mode of operation 有权
    将处理器置于高速运行模式的系统和方法

    公开(公告)号：JP2007287141A

    公开(公告)日：2007-11-01

    申请号：JP2007099182

    申请日：2007-04-05

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： RONALD HALL ,  CHRISTOPHER M ABERNATHY ,  KURT ALAN FAIST ,  VAN NORSTRAND ALBERT J JR

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/524

    Abstract: PROBLEM TO BE SOLVED: To provide a system and method for placing a processor into a gradual slow-down mode of operation. SOLUTION: The gradual slow-down mode in this system has a plurality of stages of slow-down operation of an issuing unit 330 in a processor 300 in which the issuance of instructions is slowed in accordance with a staging scheme as shown in Figure 4. The gradual slow-down of the processor allows the processor to break out of livelock conditions. Moreover, since the slow-down is gradual, the processor may flexibly avoid various degrees of livelock conditions. A mechanism of an illustrative embodiment influences the overall processor performance based on the severity of the livelock condition by taking a small performance influence on a less severe livelock condition and only increasing influence on the processor performance when the livelock condition is more severe. COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于将处理器置于逐渐减速操作模式的系统和方法。 解决方案：该系统中的逐渐减速模式在处理器300中具有发放单元330的多个阶段的减速操作，其中指令的发出根据如下所示的分段方案而变慢 图4.处理器逐渐减速使处理器能够突破活动锁定状态。 此外，由于减速是渐进的，处理器可以灵活地避免各种程度的活动锁定状况。 示例性实施例的机制通过对较不严格的活锁状态采取较小的性能影响，并且仅当活锁状态更严重时才对处理器性能的影响增加，基于活锁状态的严重性来影响整体处理器性能。 版权所有（C）2008，JPO＆INPIT

    Apparatus and method for handling data cache miss out-of-order for asynchronous pipeline
    3.
    发明专利
    Apparatus and method for handling data cache miss out-of-order for asynchronous pipeline 有权
    用于处理数据缓存的装置和方法不适用于异步管道

    公开(公告)号：JP2007207238A

    公开(公告)日：2007-08-16

    申请号：JP2007019199

    申请日：2007-01-30

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CHRISTOPHER MICHAEL ABERNATHY ,  RONALD HALL ,  BRADFORD JEFFREY POWERS ,  SHIPPY DAVID ,  HEIL TIMOTHY HUME

    IPC: G06F9/38 ,  G06F12/08

    CPC classification number: G06F9/30043 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3859 ,  G06F9/3861

    Abstract: PROBLEM TO BE SOLVED: To provide an apparatus for handling data cache misses out-of-order for a plurality of asynchronous pipelines. SOLUTION: This apparatus associates a load tag (LTAG) identifier with a load instruction, and constantly monitors load instructions across multiple pipelines as indexes to the load table data structure of the load target buffer. The load table manages the cache hits/misses, and is used to aid in the recycling of data from the L2 cache. When the load instruction is issued and the corresponding entry in the load table is seen as what is marked as "miss", the effects of issuance of the load instruction are canceled. The load instruction is stored in the load table for future reissuing to the instruction pipe line when the requested data is recycled. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供用于处理多个异步管线的无序数据高速缓存未命中的装置。 解决方案：该装置将负载标签（LTAG）标识符与加载指令相关联，并且不断监视跨多个管道的加载指令作为加载目标缓冲区的加载表数据结构的索引。 加载表管理缓存命中/未命中，并用于帮助从L2缓存中回收数据。 当发出加载指令并且将负载表中的相应条目视为标记为“未命中”的情况时，将取消发出加载指令的效果。 加载指令存储在加载表中，以便在请求的数据被回收时将来重新发布到指令管道。 版权所有（C）2007，JPO＆INPIT

    Method, information processing system, and processor for scalable status tracking of assist hardware thread
    4.
    发明专利
    Method, information processing system, and processor for scalable status tracking of assist hardware thread 有权
    方法，信息处理系统，以及辅助硬件线路可扩展状态跟踪处理器

    公开(公告)号：JP2012064215A

    公开(公告)日：2012-03-29

    申请号：JP2011202136

    申请日：2011-09-15

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： GILES ROGER FRASER ,  ARNDT RICHARD LOUIS ,  RONALD HALL

    IPC: G06F11/30

    CPC classification number: G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/485

    Abstract: PROBLEM TO BE SOLVED: To provide a method, an information processing system, and a processor for tracking an activity of an assist hardware thread with the use of an assist thread status register by an initiating hardware thread without involvement of a supervisor program.SOLUTION: A processor 100 includes an initiating hardware thread 120 (initiating HT), and initiates a first assist hardware to execute a first code segment. Next, the initiating HT sets an assist thread executing indicator (ATI) in response to initiating a first assist hardware thread 150 (AHT). An AT indicates whether the AHT is executing or not. A second AHT is initiated and starts execution of a second code segment. Subsequently, the initiating HT detects a change in the ATI and evaluates an execution result of the AHT in response to process termination of both of the first AHT and the second AHT, which is indicated by the indicator.

    Abstract translation: 要解决的问题：提供一种方法，信息处理系统和处理器，用于通过启动硬件线程使用辅助线程状态寄存器跟踪辅助硬件线程的活动，而不涉及主管程序 。 解决方案：处理器100包括启动硬件线程120（启动HT），并且启动第一辅助硬件以执行第一代码段。 接下来，启动HT响应于启动第一辅助硬件线程150（AHT）而设置辅助线程执行指示符（ATI）。 AT指示AHT是否执行。 第二个AHT被启动并开始执行第二个代码段。 随后，起始HT检测到ATI中的变化，并且响应于由指示符指示的第一AHT和第二AHT两者的过程终止来评估AHT的执行结果。 版权所有（C）2012，JPO＆INPIT

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