公开(公告)号：JP2001318730A

公开(公告)日：2001-11-16

申请号：JP2001070075

申请日：2001-03-13

Applicant: IBM

Inventor： ROSNO PATRICK LEE ,  STROM JAMES DAVID

IPC: G01R31/319 ,  G06F1/04 ,  G06F1/08 ,  G06F1/32 ,  G11C29/50 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for adjusting the operation margin or timing margin of the clocked system of a digital computer or a memory controller or the like. SOLUTION: The initial frequency or default frequency of a clock is set and the clock control settings of a duty cycle, a VCO range and a gain, etc., are also initialized and set as some kinds of defaults. Tests such as ABIST, LBIST or other function tests, etc., are executed to the clocked system and the clock frequency is increased until failing in the test. At the time of failing in the test, one or plural clock control settings are adjusted and the test is executed again at the frequency in which a fault is generated. The test is repeated while increasing the frequency until failing in the test or reaching a desired timing margin.

公开(公告)号：DE10110315C2

公开(公告)日：2003-12-04

申请号：DE10110315

申请日：2001-03-03

Applicant: IBM

Inventor： ROSNO PATRICK LEE ,  STROM JAMES DAVID

IPC: G01R31/319 ,  G06F1/04 ,  G06F1/08 ,  G06F1/32 ,  G11C29/50 ,  G11C7/00 ,  G01R27/26

Abstract: A method of adjusting the operating or timing margin of a clocked system, such as a digital computer or a memory controller, is disclosed. The method may be automated to occur upon every initial program load or can be manually adjusted for changes in frequency, operating voltages, or applications in which the timing margin is not so critical. An initial or default frequency of the clock is set. Clock control settings, such as duty cycle, VCO range and gain, etc, are also initialized and set as some default. Test, such as ABIST, LBIST or other functional tests, are performed on the clocked system and the clock frequency is incrementally increased until the tests fail. Upon failure of the tests, one or more clock control settings are adjusted and the tests are run again at the failing frequency. If the tests successfully complete, indicating no errors, the clock frequency is incremented again until the test fail. Again, the clock control settings are adjusted and the tests are repeated at increasing frequency until failure of the tests or until a desired timing margin is reached.

公开(公告)号：DE10110315A1

公开(公告)日：2001-09-27

申请号：DE10110315

申请日：2001-03-03

Applicant: IBM

Inventor： ROSNO PATRICK LEE ,  STROM JAMES DAVID

IPC: G01R31/319 ,  G06F1/04 ,  G06F1/08 ,  G06F1/32 ,  G11C29/50

Abstract: Optimization method involves monitoring system output capacity, voltage levels and devices and comparing these with threshold parameters. The system clock and/or voltages are incremented and the system retested at each step. If the desired timing parameters and outputs are met, the system has been optimized.