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公开(公告)号：JPH1065515A
公开(公告)日：1998-03-06
申请号：JP13081697
申请日：1997-05-21
Applicant: IBM
Inventor： EMEIGH ROGER D , MIKOS JAMES F , DAVID LAURENCE PEACE , STROM JAMES DAVID
IPC: H03K19/003 , H03K19/0175 , H04L25/02 , H04L12/28
Abstract: PROBLEM TO BE SOLVED: To provide a signal transmission system by matching an operation parameter of lots of output drivers stably so as to provide signal transmission controlled with high reliability. SOLUTION: A plurality of differential output drivers 30 are connected to a reference current generator 20, each output driver 30 receives almost the same copy of a reference current signal to control one operating parameter or over of each output driver 30. Lots of copies of the reference current signal are generated in the same area of an integrated circuit chip 11 thereby producing fluctuation of the respective copies of the reference current signal to minimize the process fluctuation in the chip. Each output driver 30 has a differential pair transistors (TRs) connected to ground or a power supply via a common mode resistor and the common mode resistor controls a common mode component of the driver output independently of an output voltage swing.
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公开(公告)号：JP2001318730A
公开(公告)日：2001-11-16
申请号：JP2001070075
申请日：2001-03-13
Applicant: IBM
Inventor： ROSNO PATRICK LEE , STROM JAMES DAVID
Abstract: PROBLEM TO BE SOLVED: To provide a method for adjusting the operation margin or timing margin of the clocked system of a digital computer or a memory controller or the like. SOLUTION: The initial frequency or default frequency of a clock is set and the clock control settings of a duty cycle, a VCO range and a gain, etc., are also initialized and set as some kinds of defaults. Tests such as ABIST, LBIST or other function tests, etc., are executed to the clocked system and the clock frequency is increased until failing in the test. At the time of failing in the test, one or plural clock control settings are adjusted and the test is executed again at the frequency in which a fault is generated. The test is repeated while increasing the frequency until failing in the test or reaching a desired timing margin.
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公开(公告)号：DE10110315C2
公开(公告)日：2003-12-04
申请号：DE10110315
申请日：2001-03-03
Applicant: IBM
Inventor： ROSNO PATRICK LEE , STROM JAMES DAVID
Abstract: A method of adjusting the operating or timing margin of a clocked system, such as a digital computer or a memory controller, is disclosed. The method may be automated to occur upon every initial program load or can be manually adjusted for changes in frequency, operating voltages, or applications in which the timing margin is not so critical. An initial or default frequency of the clock is set. Clock control settings, such as duty cycle, VCO range and gain, etc, are also initialized and set as some default. Test, such as ABIST, LBIST or other functional tests, are performed on the clocked system and the clock frequency is incrementally increased until the tests fail. Upon failure of the tests, one or more clock control settings are adjusted and the tests are run again at the failing frequency. If the tests successfully complete, indicating no errors, the clock frequency is incremented again until the test fail. Again, the clock control settings are adjusted and the tests are repeated at increasing frequency until failure of the tests or until a desired timing margin is reached.
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公开(公告)号：DE10110315A1
公开(公告)日：2001-09-27
申请号：DE10110315
申请日：2001-03-03
Applicant: IBM
Inventor： ROSNO PATRICK LEE , STROM JAMES DAVID
IPC: G01R31/319 , G06F1/04 , G06F1/08 , G06F1/32 , G11C29/50
Abstract: Optimization method involves monitoring system output capacity, voltage levels and devices and comparing these with threshold parameters. The system clock and/or voltages are incremented and the system retested at each step. If the desired timing parameters and outputs are met, the system has been optimized.
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