公开(公告)号：JPH097397A

公开(公告)日：1997-01-10

申请号：JP14526696

申请日：1996-06-07

Applicant: IBM

Inventor： ROBAATO DEIIN ADAMUSU ,  JIYON KONAA ,  GIYARETSUTO SUTEEBUN KOTSUHO ,  RUIJI TERUNUTSURO JIYUNIA

IPC: G11C29/12 ,  G11C29/10 ,  G11C29/36 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To obtain a self test circuit with a built-in memory array which has a programmable pattern generator to permit a definite read/white operation to an adjacent memory cell. SOLUTION: The test circuit is a test circuit having an on-chip memory array and provided with a programmable pattern generator 100 coupled to an external controller and a memory array 150. The pattern generator is provided with a read/write controller 104 for providing a read/write control to the memory array, a data generator 102 for providing data to the memory array and an address frequency controller 108. The external controller programs an adequate frequency pattern in the address frequency controller and determines a cycle count for the memory array executed by the pattern generator at each address of the memory array.

公开(公告)号：JPH0922388A

公开(公告)日：1997-01-21

申请号：JP4509096

申请日：1996-03-01

Applicant: IBM

Inventor： ROBERT DEAN ADAMS ,  CONNER JOHN ,  JIEEMUZU JIEI KOBUIINO ,  ROI CHIYAIRUZU FUREEKAA ,  GIYARETSUTO SUTEIIBUN KOTSUHO ,  ROBERTS ALAN LEE ,  HOSE RORISU SUUZA ,  RUIJI TERUNUTSURO JIYUNIA

IPC: G06F12/16 ,  G06F12/08 ,  G11C8/10 ,  G11C15/00 ,  G11C15/04 ,  G11C29/00 ,  G11C29/02 ,  G11C29/10 ,  G11C29/12 ,  G11C29/56

Abstract: PROBLEM TO BE SOLVED: To test an associated memory provided with plural memories to be tested. SOLUTION: First and second memories 10 and 12 are formed, data inside the first memory 10 include the fundamental data of at least one part of input to the second memory 12 and the data inside the first memory 10 are used so as to generate as least a part of the input to the second memory 12 by an access route from the output port of the first memory 10 to the input port of the second memory 12. First, the first memory 10 is tested independent of the second memory 12 and thereafter, preconditioned data to be used as the foundation of the input to the second memory 12 during the test of the second memory 12 are loaded to the first memory 10. Then, by generating the input to the first memory 10 during the test of the second memory 12, the second memory 12 is tested. The output of the first memory 10 becomes at least a part of test data inputted to the second memory 12.