公开(公告)号：JPH0922388A

公开(公告)日：1997-01-21

申请号：JP4509096

申请日：1996-03-01

Applicant: IBM

Inventor： ROBERT DEAN ADAMS ,  CONNER JOHN ,  JIEEMUZU JIEI KOBUIINO ,  ROI CHIYAIRUZU FUREEKAA ,  GIYARETSUTO SUTEIIBUN KOTSUHO ,  ROBERTS ALAN LEE ,  HOSE RORISU SUUZA ,  RUIJI TERUNUTSURO JIYUNIA

IPC: G06F12/16 ,  G06F12/08 ,  G11C8/10 ,  G11C15/00 ,  G11C15/04 ,  G11C29/00 ,  G11C29/02 ,  G11C29/10 ,  G11C29/12 ,  G11C29/56

Abstract: PROBLEM TO BE SOLVED: To test an associated memory provided with plural memories to be tested. SOLUTION: First and second memories 10 and 12 are formed, data inside the first memory 10 include the fundamental data of at least one part of input to the second memory 12 and the data inside the first memory 10 are used so as to generate as least a part of the input to the second memory 12 by an access route from the output port of the first memory 10 to the input port of the second memory 12. First, the first memory 10 is tested independent of the second memory 12 and thereafter, preconditioned data to be used as the foundation of the input to the second memory 12 during the test of the second memory 12 are loaded to the first memory 10. Then, by generating the input to the first memory 10 during the test of the second memory 12, the second memory 12 is tested. The output of the first memory 10 becomes at least a part of test data inputted to the second memory 12.

公开(公告)号：JP2002140892A

公开(公告)日：2002-05-17

申请号：JP2001257661

申请日：2001-08-28

Applicant: IBM

Inventor： ROBERT DEAN ADAMS ,  CONNER JOHN ,  COVINO JAMES J ,  FLAKER ROY C ,  KOCH GARRETT S ,  ROBERTS ALAN L ,  SOUSA JOSE R ,  TERNULLO JR LUIGI

IPC: G06F12/16 ,  G06F12/08 ,  G11C8/10 ,  G11C15/00 ,  G11C15/04 ,  G11C29/00 ,  G11C29/02 ,  G11C29/10 ,  G11C29/12 ,  G11C29/56

Abstract: PROBLEM TO BE SOLVED: To provide a memory system and a method in which a RAM is not required to stand by until a CAM processes a row address for a RAM. SOLUTION: This device is provided with a RAM including at least two data columns of first and second in which data is included, a gate circuit coupled to the first and the second columns and gating an output of the RAM data, and a CAM, the CAM is provided with at least two address columns including plural address positions in them, and a control circuit coupled to each address position of the first and the second address columns in the CAM and the gate circuit, sending a control signal to the gate means when a comparison address coincides with an address in the first or the second address column, and outputting RAM data from a data column address-specified by the gate means.