公开(公告)号：JPH10301794A

公开(公告)日：1998-11-13

申请号：JP8516798

申请日：1998-03-31

Applicant: IBM

Inventor： KENNETH J GOODNOW ,  CLARENCE R OGIRUBII ,  WILBUR D PRISER ,  SABASTIAN T VENTOLON

IPC: G06F9/46 ,  G06F12/08 ,  H04M3/00

Abstract: PROBLEM TO BE SOLVED: To prevent the stoppage of a processor by task changeover by predicting the next task to be processed and loading the next task to a cache memory before the execution of the task. SOLUTION: This information processing system is provided with at least one processor, that is a central processing unit(CPU) 10, the cache memory 13 provided in the CPU 10 is provided with the storage hierarchy of a single level or plural levels and the CPU 10 is provided with a task queue 42 further. The task queue 42 is provided with plural task registers 44, 46,...52 and the task registers store a task list in a time-based processing order from the present task to the next task. By using the task list, before the CPU 10 completes the processing of the present task, the point of time of loading the next task to the cache memory 13 is predicted. Also, by allocating a task ID to the respective tasks, the task is identified.