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公开(公告)号:JPH10301794A
公开(公告)日:1998-11-13
申请号:JP8516798
申请日:1998-03-31
Applicant: IBM
Inventor: KENNETH J GOODNOW , CLARENCE R OGIRUBII , WILBUR D PRISER , SABASTIAN T VENTOLON
Abstract: PROBLEM TO BE SOLVED: To prevent the stoppage of a processor by task changeover by predicting the next task to be processed and loading the next task to a cache memory before the execution of the task. SOLUTION: This information processing system is provided with at least one processor, that is a central processing unit(CPU) 10, the cache memory 13 provided in the CPU 10 is provided with the storage hierarchy of a single level or plural levels and the CPU 10 is provided with a task queue 42 further. The task queue 42 is provided with plural task registers 44, 46,...52 and the task registers store a task list in a time-based processing order from the present task to the next task. By using the task list, before the CPU 10 completes the processing of the present task, the point of time of loading the next task to the cache memory 13 is predicted. Also, by allocating a task ID to the respective tasks, the task is identified.
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公开(公告)号:SG90028A1
公开(公告)日:2002-07-23
申请号:SG1998000547
申请日:1998-03-14
Applicant: IBM
Inventor: KENNETH J GOODNOW , CLARENCE R OGILVIE , WILBUR DAVID PRICER , SEBASTIAN THEODORE VENTRONE
Abstract: A call progress analysis system is provided which is generic to any telecommunications system with which it is used due to configurable detection parameters. A signal on a channel of the telecommunications system is detected in intervals of changing frequency composition and compared to stored pattern descriptors, each of which defines a different call progress signal. In an alternative embodiment of the invention, a frequency mask is computed that is specific to a user-defined call progress analysis class. This frequency mask is used to make the DSP receiver ignore frequencies that are not part of any call progress pattern in a particular class. The frequency mask can be used in a frequency detection mode or an energy detection mode. In either mode, the detector can be customized for each channel.
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公开(公告)号:SG90108A1
公开(公告)日:2002-07-23
申请号:SG200001383
申请日:2000-03-10
Applicant: IBM
Inventor: ALVAR A DEAN , KENNETH J GOODNOW , PATRICK E PERRY , SEBASTIAN THEODORE VENTRONE
Abstract: A processor with multiple equivalent functional units for power reduction, which includes a mechanism for controlling the selection of functional units. Specifically, the processor comprises a first circuit performing a predetermined function at a first speed, a second circuit for performing the same predetermined function at a second speed, and a control system for selecting either the first or second circuit to perform the function. The control system further includes a mechanism for controlling the rate of execution of the processor instructions in the pipeline in order to compensate for the speed at which the first or second circuit was performing the predetermined function.
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