公开(公告)号：DE3176048D1

公开(公告)日：1987-04-30

申请号：DE3176048

申请日：1981-06-03

Applicant: IBM

Inventor： SAGER GORDON STANLEY ,  SUTTON ARTHUR JAMES

IPC: G06F12/16 ,  G06F11/22 ,  G11C29/12 ,  G11C29/48 ,  G11C29/56 ,  G11C29/00

Abstract: The system has plural sets of BSMs in which any set can be operationally fenced from system operation in order to validate any BSM in the fenced set, while the system normally operates with the unfenced set(s) of BSMs comprising main storage. Each BSM set has a BSM controller (BSC) which is integrated with a hardware BSM tester (5V). All cells in and the addressing circuits to any BSM can be tested by incrementing line addresses through the BSM while comparing a true pattern and then a complement pattern, and then decrementing line addresses through the BSM comparing the complement pattern and then the true pattern. The BSM testers use level sensitive scan design (LSSD) circuits in the BSM controller to serially communicate with a system service processor in response to commands from the service processor and interrupt signals from the BSM tester. A marker mask in each BSM tester permits BSM testing continuity after each interrupt signal. Between commands, the BSM tester can operate automatically and in parallel with the service processor.