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公开(公告)号：DE3279965D1
公开(公告)日：1989-11-02
申请号：DE3279965
申请日：1982-10-18
Applicant: IBM
Inventor： MOORE BRIAN BARRY , RODELL JOHN TED , SUTTON ARTHUR JAMES , VOWELL JEFF D
Abstract: This is a system which is used to perform reconfiguration of storage elements in order to permit removal of one or more of the elements for servicing or other reasons. If a storage element that is to be taken off line contains material that is crucial to the continued operation of the system, that material is copied to appropriate areas in other storage elements. After all crucial material has been copied to alternate locations, the original storage element can be taken off line for servicing or other purposes.
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公开(公告)号：DE69219657T2
公开(公告)日：1997-10-23
申请号：DE69219657
申请日：1992-02-08
Applicant: IBM
Inventor： SUTTON ARTHUR JAMES
Abstract: Completes on a another CPU the execution of a program, or program task, terminated by a processor error on a first CPU without re-executing any successfully-completed instructions and without any abnormal ending being provided to the program. The continued program need not have any built-in recovery or correction code. Predetermined register contents in the failed processor are stored (92, 93) in predetermined storage locations by the failing processor (CPUf) or by a service processor (SP) when the failing processor (CPUf) has not been able to store this information. The predetermined contents saved from the failed processor are defined by the system architecture for saving an interruption of a program to enable the continuation of execution of the program after restoring the contents of PSWs, CRs, FPRs, GPRs, ARs, etc. if using the ESA/370 architecture. When a failed processor (CPUf) is detected, the SP issues (33) an external interruption to other processors (CPUh) in the system that are operable for continuing the execution of the failed processor task after the required information is stored. Special indicators (MCIC) are stored in predetermined places (PSA) in the system and/or microcode memory that is accessible to the SP and to the healthy processors (CPUh) in the system selectable for continuing the task's execution.
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公开(公告)号：DE69219657D1
公开(公告)日：1997-06-19
申请号：DE69219657
申请日：1992-02-08
Applicant: IBM
Inventor： SUTTON ARTHUR JAMES
Abstract: Completes on a another CPU the execution of a program, or program task, terminated by a processor error on a first CPU without re-executing any successfully-completed instructions and without any abnormal ending being provided to the program. The continued program need not have any built-in recovery or correction code. Predetermined register contents in the failed processor are stored (92, 93) in predetermined storage locations by the failing processor (CPUf) or by a service processor (SP) when the failing processor (CPUf) has not been able to store this information. The predetermined contents saved from the failed processor are defined by the system architecture for saving an interruption of a program to enable the continuation of execution of the program after restoring the contents of PSWs, CRs, FPRs, GPRs, ARs, etc. if using the ESA/370 architecture. When a failed processor (CPUf) is detected, the SP issues (33) an external interruption to other processors (CPUh) in the system that are operable for continuing the execution of the failed processor task after the required information is stored. Special indicators (MCIC) are stored in predetermined places (PSA) in the system and/or microcode memory that is accessible to the SP and to the healthy processors (CPUh) in the system selectable for continuing the task's execution.
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公开(公告)号：DE3176048D1
公开(公告)日：1987-04-30
申请号：DE3176048
申请日：1981-06-03
Applicant: IBM
Inventor： SAGER GORDON STANLEY , SUTTON ARTHUR JAMES
Abstract: The system has plural sets of BSMs in which any set can be operationally fenced from system operation in order to validate any BSM in the fenced set, while the system normally operates with the unfenced set(s) of BSMs comprising main storage. Each BSM set has a BSM controller (BSC) which is integrated with a hardware BSM tester (5V). All cells in and the addressing circuits to any BSM can be tested by incrementing line addresses through the BSM while comparing a true pattern and then a complement pattern, and then decrementing line addresses through the BSM comparing the complement pattern and then the true pattern. The BSM testers use level sensitive scan design (LSSD) circuits in the BSM controller to serially communicate with a system service processor in response to commands from the service processor and interrupt signals from the BSM tester. A marker mask in each BSM tester permits BSM testing continuity after each interrupt signal. Between commands, the BSM tester can operate automatically and in parallel with the service processor.
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