公开(公告)号：DE3279236D1

公开(公告)日：1988-12-29

申请号：DE3279236

申请日：1982-05-24

Applicant: IBM

Inventor： BAUM RICHARD IRWIN ,  SAKALAY FREDERICK ELIAS

IPC: G06F11/34

Abstract: The disclosure provides a hardware monitor device connectable to a large high speed processor in a uniprocessor or multiprocessor system to correlate software activity to hardware activity by capturing samples of instruction addresses (which are architecturally visible to the software) that cause the occurrence of the monitored activity manifested by electrical signals in processor circuit (e.g. setting of a latch), and recording the instruction addresses with a designation of the monitored event(s), e.g. cache miss. The embodiment samples which instructions are to be captured by selecting one per N number of samplings of a specified event to be monitored. An MP embodiment makes possible the monitoring of software and/or hardware relationships between processors in a multiprocessor by connecting a monitor to each processor being monitored, and interconnecting an event capture signal generated in one processor monitor (master) to control the capture recording means in another processor monitor (slave), so that the recorded information can indicate if the instruction in one processor is responsible for an event occurring in the other processor. A personalization register in each monitor is loaded by a control processor with the identifier of the processor being monitored, the sample count value N, a designation of the particular capturable event which is to control the capture of its causative instruction address, and a designation of other events or conditions whose current state will be indicated as part of the captured data.