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    2.
    发明专利
    未知

    公开(公告)号：DE69231611D1

    公开(公告)日：2001-02-01

    申请号：DE69231611

    申请日：1992-10-30

    Applicant: IBM

    Inventor： BAUM RICHARD IRWIN ,  PLAMBECK KENNETH ERNEST ,  SCALZI CASPER ANTHONY ,  SCHMALZ RICHARD JOHN ,  SINHA BHASKAR

    IPC: G06F12/10 ,  G06F12/02

    Abstract: A method and means of translating a large logical address as a large virtual address (LVA) when dynamic address translator (DAT) is on and for using the large logical address as a large real address (LRA) when DAT (33) is off. This LVA or LRA is used for locating data and instructions in a computer memory. Each LVA is separated into three concatenated parts: a highest-order part (ADEN) for indexing into an access directory (AD) to locate an entry (ADE) for locating one access list (AL); an intermediate part (ALEN) for indexing into a selected AL to access an entry (ALE) that enables location of an associated conventional address translation table which represents a conventional size virtual address space; and a low-order DAT VA part having the same size as the conventional type of virtual address. The low-order DAT VA part is translated by the associated translation table (48). This address translation of the low-order (DAT VA) part provides a real address that represents the translation of the LVA. The LVAs map into a large virtual address space (LVAS) represented by the sequence of valid ALEs in the set of ALs respectively represented by the sequence of valid ADEs in the AD. The sequence of ADEs in the AD respectively locate the ALs containing the ALEs which represent the LVAS. Thus, the range of LVAs (starting from zero) in the LVAS maps to the respective ALEs in the set of ALs. Each AL may contain a respective offset of ALEs that are not part of the LVAS.

    7.
    发明专利
    未知

    公开(公告)号：DE69231611T2

    公开(公告)日：2001-07-05

    申请号：DE69231611

    申请日：1992-10-30

    Applicant: IBM

    Inventor： BAUM RICHARD IRWIN ,  PLAMBECK KENNETH ERNEST ,  SCALZI CASPER ANTHONY ,  SCHMALZ RICHARD JOHN ,  SINHA BHASKAR

    IPC: G06F12/10 ,  G06F12/02

    Abstract: A method and means of translating a large logical address as a large virtual address (LVA) when dynamic address translator (DAT) is on and for using the large logical address as a large real address (LRA) when DAT (33) is off. This LVA or LRA is used for locating data and instructions in a computer memory. Each LVA is separated into three concatenated parts: a highest-order part (ADEN) for indexing into an access directory (AD) to locate an entry (ADE) for locating one access list (AL); an intermediate part (ALEN) for indexing into a selected AL to access an entry (ALE) that enables location of an associated conventional address translation table which represents a conventional size virtual address space; and a low-order DAT VA part having the same size as the conventional type of virtual address. The low-order DAT VA part is translated by the associated translation table (48). This address translation of the low-order (DAT VA) part provides a real address that represents the translation of the LVA. The LVAs map into a large virtual address space (LVAS) represented by the sequence of valid ALEs in the set of ALs respectively represented by the sequence of valid ADEs in the AD. The sequence of ADEs in the AD respectively locate the ALs containing the ALEs which represent the LVAS. Thus, the range of LVAs (starting from zero) in the LVAS maps to the respective ALEs in the set of ALs. Each AL may contain a respective offset of ALEs that are not part of the LVAS.

    8.
    发明专利
    未知

    公开(公告)号：AT198381T

    公开(公告)日：2001-01-15

    申请号：AT92118610

    申请日：1992-10-30

    Applicant: IBM

    Inventor： BAUM RICHARD IRWIN ,  PLAMBECK KENNETH ERNEST ,  SCALZI CASPER ANTHONY ,  SCHMALZ RICHARD JOHN ,  SINHA BHASKAR

    IPC: G06F12/10 ,  G06F12/02

    Abstract: A method and means of translating a large logical address as a large virtual address (LVA) when dynamic address translator (DAT) is on and for using the large logical address as a large real address (LRA) when DAT (33) is off. This LVA or LRA is used for locating data and instructions in a computer memory. Each LVA is separated into three concatenated parts: a highest-order part (ADEN) for indexing into an access directory (AD) to locate an entry (ADE) for locating one access list (AL); an intermediate part (ALEN) for indexing into a selected AL to access an entry (ALE) that enables location of an associated conventional address translation table which represents a conventional size virtual address space; and a low-order DAT VA part having the same size as the conventional type of virtual address. The low-order DAT VA part is translated by the associated translation table (48). This address translation of the low-order (DAT VA) part provides a real address that represents the translation of the LVA. The LVAs map into a large virtual address space (LVAS) represented by the sequence of valid ALEs in the set of ALs respectively represented by the sequence of valid ADEs in the AD. The sequence of ADEs in the AD respectively locate the ALs containing the ALEs which represent the LVAS. Thus, the range of LVAs (starting from zero) in the LVAS maps to the respective ALEs in the set of ALs. Each AL may contain a respective offset of ALEs that are not part of the LVAS.

    9.
    发明专利
    未知

    公开(公告)号：DE3854616T2

    公开(公告)日：1996-06-13

    申请号：DE3854616

    申请日：1988-12-12

    Applicant: IBM

    Inventor： BAUM RICHARD IRWIN ,  BORDEN TERRY LEE ,  BUTWELL JUSTIN RALPH ,  CLARK CARL EDWARD ,  GANEK ALAN GEORGE ,  LUM JAMES ,  MALL MICHAEL GERARD ,  PAGE DAVID RICHARD ,  PLAMBECK KENNETH ERNST ,  SCALZI CASPER ANTHONY ,  SCHMALZ RICHARD JOHN

    IPC: G06F12/08 ,  G06F9/46 ,  G06F12/10 ,  G06F12/14 ,  G06F21/24 ,  G06F12/02

    Abstract: A program authorization mechanism for authorizing access to an address space in the main memory of a computer system by a program being run under a multiple address space facility. An access-list entry is associated with each address space, each access-list entry being designated by an access-list-entry token contained in an access register. Each access-list entry includes a private indicator which indicates if the associated address space can be accessed by all programs from this access-list entry or if the associatd address space can only be accessed by an authorized program. For a program to be authorized, an extended authorization index in a control register must match an access-list extended authorization index in the access-list entry, or the extended authorization index value must be authorized in an authority table associated with the address space. An instruction for testing a given extended authorization index for a given access-list-entry is also disclosed.

    10.
    发明专利
    未知

    公开(公告)号：DE69021710T2

    公开(公告)日：1996-04-18

    申请号：DE69021710

    申请日：1990-10-31

    Applicant: IBM

    Inventor： BAUM RICHARD IRWIN ,  BROTMAN CHARLES H ,  RYMARCZYK JAMES WALTER

    IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  G06F11/14 ,  G06F11/20 ,  G06F13/00 ,  G06F13/36 ,  G06F15/173

    Abstract: A large number of processing elements (604) (e.g. 4096) are interconnected by means of a high bandwidth switch (606). Each processing element (604) includes one or more general purpose microprocessors (1202), a local memory (1210) and a DMA controller (1206) that sends and receives messages through the switch (606) without requiring processor intervention. The switch (606) that connects the processing elements is hierarchical and comprises a network of clusters. Sixtyfour processing elements (604) can be combined to form a cluster and and sixtyfour clusters can be linked by way of a Banyan network. Messages are routed through the switch (606) in the form of packets which include a command field, a sequence number, a destination address, a source address, a data field (which can include subcommands), and an error correction code. Error correction is performed at the processing elements. If a packet is routed to a non-present or non-functional processor, the switch (606) reverses the source and destination field and returns the packet to the sender with an error flag. If the packet is misrouted to a functional processing element (604), the processing element (604) corrects the error and retransmits the packet through the switch (606) over a different path. In one embodiment, each processing element can be provided with a hardware accelerator for database functions. In this embodiment, the multiprocessor of the present invention can be employed as a coprocessor to a 370 host and used to perform database functions.

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