公开(公告)号：JPH06223572A

公开(公告)日：1994-08-12

申请号：JP24806793

申请日：1993-10-04

Applicant: IBM

Inventor： SAN HOO DONGU ,  KIRIHATA TOSHIAKI ,  HIYUN JIYON SHIN ,  SUNANAGA TOSHIO ,  TAIRA YOICHI ,  RUISU MADEISON TERUMAN

IPC: G11C11/409 ,  G11C11/407 ,  G11C11/4094

Abstract: PURPOSE: To reduce the power dissipating amounts of a bit line by providing a DRAM structure using a variable precharge voltage detecting technique. CONSTITUTION: In the end of a row address storage(RAS) cycle, a bit line 10 and a complementary bit 12 are short-circuited, and short-circuited through a line 32 with VEQ by equalizing devices 18, 20, and 22, and balancing is operated by bit line precharge in the next RAS cycle. This voltage is higher than the precharge voltage in the previous cycle. When a capacitance 88 of a memory cell to which access is performed stores 0V, the bit line precharge voltage is made lower than that in the previous RAS cycle. When a high level is stored in the cell capacitance of the cell connected with a word line and accessed in each following cycle, the same sequence is repeated in the following RAS cycle, and the bit line precharge voltage is increased in each cycle. Then, a bit line power can not be drawn from a DRAM power source by the balancing with a bit line pair voltage.