公开(公告)号：DE2844216A1

公开(公告)日：1979-05-23

申请号：DE2844216

申请日：1978-10-11

Applicant: IBM DEUTSCHLAND

Inventor： BECKENHAUER ROBERT LEE ,  SCHAEUBLE WERNER JOSEF

IPC: G06F11/10 ,  G11B20/12 ,  G11B20/14 ,  H03M5/12 ,  H03M7/14 ,  H03M7/40 ,  H04L7/00 ,  H04L25/49 ,  H03K13/00 ,  G11B5/012

Abstract: SYNC PATTERN ENCODING SYSTEM FOR RUN-LENGTH LIMITED CODES A system which employs a parallel to serial converter and a serial shift register encoder for encoding a multibyte sync pattern in a fixed rate variable word length run-length limited code wherein less than a single character of data is supplied to the encoder from the parallel to serial converter to encode the multibyte sync pattern. The system provides for feeding a first portion of the encoded sync pattern back to the encoder through a serial decoder which provides a serial bit stream that is identical to the initial pattern provided to the encoder. Suitable control circuitry is employed to control the phasing of the end of the initial bit stream and the beginning of the decoded bit stream fed back to the encoder. Once the feedback path is established, the total length of the encoded sync pattern is independent of the single character initially supplied to the encoder.

公开(公告)号：DE2965653D1

公开(公告)日：1983-07-21

申请号：DE2965653

申请日：1979-06-01

Applicant: IBM

Inventor： HODGES PAUL ,  SCHAEUBLE WERNER JOSEF ,  SHAFFER PAUL LEE

IPC: G06F11/10 ,  G06F12/16 ,  H03M13/00 ,  H03M13/13 ,  H03M13/27 ,  G11B5/00 ,  G11C7/00

公开(公告)号：DE2962275D1

公开(公告)日：1982-04-15

申请号：DE2962275

申请日：1979-06-01

Applicant: IBM

Inventor： CARLTON JAMES EARNEST ,  SCHAEUBLE WERNER JOSEF

IPC: H03M9/00 ,  G06F3/06 ,  G06F13/00 ,  H04L29/00 ,  G06F13/04 ,  G06F5/04 ,  G11B5/012

Abstract: The invention concerns a disk file controller for the transfer of data from a parallel by bit interface to a serial by bit disk file interface. … A data channel has a data register (9), serializing and deserializing means (50 and 53) and a variable frequency oscillator to transfer parallel by bit data received by the register (9) from a DCI BUS OUT to be recorded serially by bit on a disk file. Alternatively the data channel receives serial by bit data read from a disk file and transfers it through the data register (9) in parallel by bit form to a DCI BUS IN. The several units of the data channel are controlled by a control register (28) supplied from a microprocessor (6). The microprocessor receives data selectively from the DCI BUS OUT and from the data register (9). Changes in format of the disk file data can be accommodated by the microprocessor (6) without need to change special purpose formatting hardware.

公开(公告)号：DE2961671D1

公开(公告)日：1982-02-18

申请号：DE2961671

申请日：1979-06-01

Applicant: IBM

Inventor： CARLTON JAMES EARNEST ,  SCHAEUBLE WERNER JOSEF

IPC: G06F11/00 ,  G06F13/00 ,  G06F13/42 ,  G06F13/04 ,  H04L1/00

Abstract: The invention concerns the transmission of data from a transmitting control unit to a disk file controller through an interface cable the length of which may vary from one installation to another thereby varying the propagation delay through the cable from one installation to another. A SYNC IN signal from an AND gate (26) of the disk file controller is used to request data from the control unit. A SYNC OUT signal is returned by the control unit. A clock generator supplies bit timing signals BIT 0 to BIT 7 to a selector (24) and the selector issues a gating signal to an AND gate (31) to generate a SYNC IN signal at a selected one of the bit times as determined by a byte of control data contained in a register (22). The bit time is selected to account for the propagation delay of the interface cable such that the resultant SYNC OUT signal is returned at a desired bit time appropriate for recording data at a predefined location on a moving recording disk.